Category: Uncategorized

Xiaoyu Sun received SRC TECHCON Student Presentation Award in Austin, TX, Sep. 2019.

Read the story here: https://ascent.nd.edu/news/xiaoyu-sun-georgia-tech-wins-student-presentation-award-at-techcon-2019/

Our IEDM work on ferroelectric transistor based synaptic cell design was cited by this industry perspective article from Semiconductor Engineering. This work was also highlighted by IEDM 2018 public press and was nominated for the best student paper. This research is sponsored by SRC JUMP program (ASCENT led by Notre Dame). See this nice article at

What’s the Right Path For Scaling?

Reference as below:

X. Sun, et al., “Exploiting hybrid precision for training and inference: a 2T-1FeFET based analog synaptic weight cell,” IEEE International Electron Devices Meeting (IEDM) 2018, San Francisco, USA

Our group in collaboration with researchers from University Notre Dame, Samsung and Tsinghua University will present 4 papers in IEDM, San Francisco, December 2018. These papers are titled:

1. X. Sun, et al., “Exploiting hybrid precision for training and inference: a 2T-1FeFET based analog synaptic weight cell,” IEEE International Electron Devices Meeting (IEDM) 2018, San Francisco, USA (highlight paper and nominated for the best student paper).
2. N. Xu, et al., “STT-MRAM design technology co-optimization for hardware neural networks,” IEEE International Electron Devices Meeting (IEDM) 2018, San Francisco, USA.
3. M. Zhao, et al., “Characterizing endurance degradation of incremental switching in analog RRAM for neuromorphic systems,” IEEE International Electron Devices Meeting (IEDM) 2018, San Francisco, USA.
4. Y. Lin, et al., “Demonstration of generative adversarial network by intrinsic random noises of analog RRAM devices,” IEEE International Electron Devices Meeting (IEDM) 2018, San Francisco, USA.

Our group in collaboration with National Tsinghua University (Taiwan) and Tsinghua University will present 2 papers in ISSCC, San Francisco, February, 2019. These papers are titled:

1. X. Si, et al. “A twin-8T SRAM computation-in-memory macro for multiple-bit CNN-based machine learning,” IEEE International Solid-State Circuits Conference (ISSCC) 2019, San Francisco, USA
2. Y. Pang, et al. “A reconfigurable RRAM physical unclonable function utilizing post-process randomness source with < 6E-6 nature bit error rate,” IEEE International Solid-State Circuits Conference (ISSCC) 2019, San Francisco, USA