Please check out Prof. Yu’s new textbook if you are interested in basics and emerging trends for SRAM, DRAM, NAND, and emerging memories.
S. Yu, Semiconductor Memory Devices and Circuits, Publisher: CRC Press/Taylor & Francis, 2022. [Link]
Accompanying video lectures are available at YouTube Link
This year we have 5 papers are accepted by IEEE Symposium on VLSI Technology and Circuits, one of the premier conferences in the microelectronics! We have two collaborative papers with Notre Dame and one collaborative paper with Purdue.
- G. Choe, P. V. Ravindran, A. Lu, J. Hur, M. Lederer, A. Reck, S. Lombardo, N. Afroze, J. Kacher, A. I. Khan, S. Yu, “Machine learning assisted statistical variation analysis of ferroelectric transistors: from experimental metrology to predictive modeling,” IEEE Symposium on VLSI Technology and Circuits (VLSI) 2022, Hawaii, USA.
- H. Jiang, W. Li, S. Huang, S. Yu, “A 40nm analog-input ADC-free compute-in-memory RRAM macro with pulse-width modulation between sub-arrays,” IEEE Symposium on VLSI Technology and Circuits (VLSI) 2022, Hawaii, USA.
- K. A. Aabrar, S. G. Kirtania, A. Lu, A. Khanna, W. Chakraborty, M. San Jose, S. Yu, S. Datta, “A thousand state superlattice(SL) FeFET analog weight cell,” IEEE Symposium on VLSI Technology and Circuits (VLSI) 2022, Hawaii, USA.
- A. Khanna, H. Ye, Y. Luo, G. Bajpai, M. San Jose, W. Chakraborty, S. Yu, P. Fay, S. Datta, “BEOL compatible ferroelectric routers for run-time reconfigurable compute-in-memory accelerators,” IEEE Symposium on VLSI Technology and Circuits (VLSI) 2022, Hawaii, USA.
- X. Lyu, P. R. Shrestha, M. Si, P. Wang, J. Li, K. P. Cheung, S. Yu, P. D. Ye, “Determination of domain wall velocity and nucleation time by switching dynamics studies of ferroelectric Hafnium Zirconium oxide,” IEEE Symposium on VLSI Technology and Circuits (VLSI) 2022, Hawaii, USA.
Prof. Yu has been named as a Distinguished Lecturer for the IEEE Electron Devices Society (EDS), with the following seminar available:
Landscape of Synaptic Weight Memories
see news article at https://www.ece.gatech.edu/news/651593/yu-appointed-ieee-eds-distinguished-lecturer
Our lab have three PhD student positions available for Fall 2023, we are looking for candidates with strong experiences in the following area: 1) advanced logic and memory device characterization and modeling (TCAD/DTCO); 2) digital and mixed-signal circuit design with tape-out experiences; 3) machine learning algorithm and hardware co-design. Please send me your resume and cover letter for evaluation and apply the Georgia Tech ECE PhD program before the application deadline in mid-December 2022.
Our lab does not have postdoc opening at this moment. But if you think your educational background and research experiences are truly outstanding and could fit in one of the three areas mentioned above in the PhD hiring, you are encouraged to contact me for special consideration.
Our lab does not accept or host international visiting students or remote interns.
Our lab will host the visiting engineers from our industry sponsors.
Due to the high volume of inquiry, I may not reply to your email if your background does not fit with our on-going research projects.
Since the COVID-19 pandemic, Prof. Shimeng Yu has been invited for the many virtual presentations at various conferences. If you are interested in the recent trends in RRAM, ferroelectric memories, and in-memory computing, please check this Youtube channel for recorded talks.