Services

Prof. Yu is actively participating in the professional services:

Senior Member, IEEE 

  • IEEE Electron Devices Society (EDS)
  • IEEE Solid-State Circuits Society (SSCS)
  • IEEE Circuits and Systems Society (CASS)
  • IEEE Council on Electronic Design Automation (CEDA)
  • ACM Special Interest Group on Design Automation (SIGDA)

IEEE Technical Committee

  • VLSI Technology and Circuits, IEEE Electron Devices Society (EDS), 2018-2021
  • Nanoelectronics and Gigascale Systems,  IEEE Circuits and Systems Society (CASS), 2015-now, as secretary 2021-2022.

IEEE Local Chapter

  • Vice Chair, IEEE Atlanta SSCS/CASS Joint Chapter, since 2021

Editorial Service:

  • Associate Editor, IEEE Electron Device Letters, 2021-now
  • Associate Editor, IOP Journal of Semiconductors, 2021-now
  • Associate Editor, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2019-now
  • Guest Editor, special issue on “Novel Materials, Devices and Solutions for Brain-Inspired Sensing and Computing”, Frontiers in Neuroscience, 2021
  • Guest Editor, special issue on “Symposium on VLSI Technology”, IEEE Transactions on Electron Devices, 2021
  • Guest Editor, special issue on “Nonvolatile Memory for Efficient Implementation of Neural/Neuromorphic Computing”, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2019
  • Guest Editor, special issue on “Exploratory Devices and Circuits for Compute-in-Memory”, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2020
  • Guest Editor, special issue on “Monolithic 3D Integration for Energy-Efficient Computing”, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2021
  • Conference Organizing Committee:

    • Publication Chair, IEEE Symposium on VLSI Technology 2021-2022
    • Award Committee, IEEE Electron Devices Technology and Manufacturing (EDTM) Conference 2021
    • Special Session Co-Chair, IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) 2021-2022
    • Publication Chair, IEEE Non-Volatile Memory Technology Symposium (NVMTS) 2019

    Technical Program Committee:

    • IEEE Symposium on VLSI Technology 2020-2022
    • IEEE Electron Devices Technology and Manufacturing (EDTM) Conference 2021-2022, Track Chair 2021-2022
    • IEEE International Reliability Physics Symposium (IRPS) 2019-2022, Track Chair 2021
    • IEEE International Electron Devices Meeting (IEDM) 2017-2018
    • IEEE Silicon Nanoelectronics Workshop (SNW) 2020
    • MRS Electronic Materials Conference (EMC) 2015-2016
    • ACM/IEEE Design, Automation & Test in Europe (DATE) 2021-2022
    • ACM/IEEE International Conference on Computer-Aided-Design (ICCAD) 2018-2020, Track Chair 2020
    • ACM/IEEE Design Automation Conference (DAC) 2017-2019
    • IEEE Symposium on Circuits and Systems (ISCAS) 2015-2017, 2022
    • ACM Great Lakes Symposium on VLSI (GLSVLSI) 2015-2016
    • ACM/IEEE International Symposium on Nanoscale Architectures (NANOARCH) 2016-2017
    • IEEE International Conference on Computer Design (ICCD) 2017
    • IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST) 2017

    Keynote/Plenary Speech:

    • S. Yu, “RRAM for Compute-in-Memory: From Inference to Training”, Keynote Speech (virtual), IEEE Asia Pacific Conference on Circuits & Systems (APCCAS), Nov. 2021.
    • S. Yu, “Compute-in-Memory: From Device Innovation to 3D System Integration”, Plenary Talk, IEEE European Solid-State Device Research Conference (ESSDERC), Sep. 2021.
    • S. Yu, “Recent Progresses of Compute-in-Memory for Deep Learning Inference Engine”, virtual overview lectureIEEE International Symposium on Circuits and Systems (ISCAS), May 2021.
    • S. Yu, “Monolithic 3D Integration of AI Accelerators,” Keynote Speech (virtual), SiP Global Summit at SEMICON Taiwan, Sep. 2020.
    • S. Yu, “Neuro-Inspired Computing with Nanoelectronic Devices: Experimental Progresses and Modeling Opportunities”, Plenary Talk, IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Udine, Italy, Sep. 2019.
    • S. Yu, “Emerging Non-Volatile Memory’s Applications in Neuro-Inspired Computing and Hardware Security,” Keynote Speech, IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Hangzhou, China, Jul. 2019.

    Short Courses/Tutorials:

    • S. Yu, “NeuroSim: A Benchmark Framework of Compute-in-Memory Hardware Accelerators from Devices/Circuits to Architectures/Algorithms”, Tutorial, IEEE International Symposium on Circuits and Systems (ISCAS), May 2022.
    • S. Yu, “3D FeFET for In-Memory Computing: From BEOL Integration to 3D NAND”, IEEE International Memory Workshop (IMW), Virtual Tutorial, May 2021.
    • S. Yu, “Analog Memory Needs for AI”, IEEE International Electron Devices Meeting (IEDM), Virtual Short Course, Dec. 2020.
    • S. Yu, “Compute-in-Memory for Deep Learning Accelerator: Benchmark and Monolithic 3D Integration”, IEEE European Solid-State Circuits Research Conference (ESSCIRC), Virtual Educational Event, Sep. 2020.
    • S. Yu, “Compute-in-Memory Prototype Chips from SRAM to RRAM”, ACM/IEEE Design Automation Conference (DAC), Virtual Tutorial, Jul. 2010.
    • S. Yu, “Compute-in-Memory: Circuits and Architectures”, Design Automation Summer School (DASS) at ACM/IEEE Design Automation Conference (DAC), Las Vegas, NV, Jun. 2019.
    • S. Yu, “Neuro-inspired Hardware from Materials/Devices/Circuits to Architectures/Algorithms”, Institute of Microelectronics, A*STAR, Singapore, Mar. 2019.
    • S. Yu, “Neuro-inspired Computing using Resistive Synaptic Devices: Challenges and Prospects,” IEEE European Solid-State Device Research Conference (ESSDERC),  Leuven, Belgium, Sep. 2017.
    • S. Yu, “Emerging Non-volatile Memory (NVM) based Computing System,” IEEE Electron Devices Technology and Manufacturing (EDTM), Toyama, Japan, Feb. 2017.

    Panelist/Moderator/Interviewee:

    • S. Yu, SRC Spring 2021 Tech Forum on the 2030 Semiconductor Agenda, virtual, May 2021.
    • S. Yu, NSF Workshop on Future of Semiconductors: Devices to Systems for In-Memory Computing, virtual, May 2021.
    • S. Yu, Reflections from an EDS Young Professional, IEEE Electron Devices Society Newsletter, vol. 28, no. 2, April 2021.
    • S. Yu, NSF Workshop on Micro/Nano Circuits and Systems Design and Design Automation: Challenges and Opportunities, virtual, Dec. 2020.
    • S. Yu, NSF Workshop on Machine Learning Hardware Breakthroughs Towards Green AI and Ubiquitous On-Device Intelligence, virtual, Nov. 2020.
    • S. Yu, “The Impact of AI to the Technology World, Mainly from Device and Design Perspectives,” IEEE International Conference on Solid-State and Integrated Circuits Technology (ICSICT), virtual, Nov. 2020.
    • S. Yu, “Devices and Materials Requirements for Artificial Intelligence”, SRC/SIA/DOE Decadal Plan for Semiconductors, Workshop on the New Compute Trajectories for Energy-Efficient Computing, Livermore, CA, Oct. 2019.
    • S. Yu, “Compute-in-Memory with RRAM Technologies,” C-BRIC Workshop at Design Automation Conference, Las Vegas, NV, Jun. 2019.
    • S. Yu, “Technologies for AI Chips – Challenges and Opportunities”, China Semiconductor Technology International Conference (CSTIC), Shanghai, China, Mar. 2019.
    • S. Yu, “Nano-Device and Architecture Interaction in Machine/Deep Learning”, NSF Nano Grantees Conference, Arlington, VA, Dec. 2017.
    • S. Yu, IEEE Electron Devices Society’s Women in Engineering and Young Professionals Career Panel, San Francisco, CA, Dec. 2017.
    • S. Yu, NSF CAREER Workshop at Arizona State University, Tempe, AZ, Mar. 2016.

    Invited Presentations/Seminars:

    • S. Yu, “Landscape of Synaptic Weight Memories”, Wayne State University, virtual, Nov. 2021.
    • S. Yu, “3D NAND based Compute-in-Memory”, Samsung Forum, virtual, Nov. 2021.
    • S. Yu, “In-Memory Computing Benchmarking and Future Trends”, Workshop at DARPA Electronics Resurgence Initiative (ERI) Summit, virtual, Oct. 2021.
    • S. Yu, “Circuit Design and Silicon Prototypes for Compute-in-Memory for Deep Learning Inference Engine,” Rutgers University Efficient AI (REFAI) Seminar, virtual, Sep. 2021.
    • S. Yu, “NeuroSim: A Benchmark Framework of Compute-in-Memory Hardware Accelerators from Devices/Circuits to Architectures/Algorithms,” Taipei Chapter of the IEEE Circuits and Systems Society, webinar, Sep. 2021.
    • S. Yu, “Circuit Design and Silicon Prototypes for Compute-in-Memory for Deep Learning Inference Engine,” Seoul Chapter of the IEEE Circuits and Systems Society, webinar, Jun. 2021.
    • S. Yu, “Ferroelectric Transistors for Synaptic Devices: Challenges and Prospects”, 3rd International Symposium on Memory Devices for Abundant Data Computing, hosted by Hong Kong Polytechnic University, virtual, May 2021.
    • S. Yu, “Challenges and Opportunities of Deep Neural Network Training or Inferencing with Synaptic Devices”, Workshop on Systems and Architectures for Robust Software 2.0 at ACM Architectural Support for Programming Languages and Operating Systems (ASPLOS), virtual, Apr. 2021.
    • S. Yu, “Microelectronics: From Materials to Circuits”, Georgia Tech CHIPS Act Faculty Workshop, virtual, Apr. 2021.
    • S. Yu, “Introduction to NeuroSim: A Benchmark Tool for Compute-in-Memory Accelerator”, Brain Inspired Computing Workshop by University of Sheffield and Indian Institute of Technology, Roorkee, virtual, Mar. 2021.
    • S. Yu, “Circuit Design and Silicon Prototypes for Compute-in-Memory for Deep Learning Inference Engine,” Toronto Chapter of the IEEE Circuits and Systems Society, webinar, Mar. 2021.
    • S. Yu, “Compute-in-Memory with Emerging Nonvolatile-Memories: Challenges and Prospects”, Santa Clara Valley-San Francisco Chapter of the IEEE Electron Devices Society, webinar, Jan. 2021.
    • S. Yu, “Compute-in-Memory for Deep Learning Accelerator: Prototyping and Benchmarking”, Northrop Grumman, Annual University Research Symposium, webinar, Oct. 2020.
    • S. Yu, “Benchmarking and Prototyping Compute-in-Memory Accelerators with Emerging Non-volatile Memories”, SRC e-workshop, Oct. 2020.
    • S. Yu, “Ferroelectric Transistors for Synaptic Devices: Challenges and Prospects,” ECS Pacific Rim Meeting (PRiME), virtual, Oct. 2020.
    • S. Yu, “Monolithic 3D Integration of AI Accelerators,” Keynote Speech (virtual), SiP Global Summit at SEMICON Taiwan, Sep. 2020.
    • S. Yu, “Compute-in-Memory for AI: From Inference to Training,” International Symposium on VLSI Design, Automation and Test (VLSI-DAT), virtual, Hsinchu, Taiwan, Aug. 2020.
    • S. Yu, “Compute-in-Memory for Deep Learning Accelerator: Challenges and Prospects”, Google Silicon Forum, webinar, Jul. 2020.
    • S. Yu, “Resistive Devices and Circuits for Neuro-Inspired Computing,” IEEE Electron Devices Society (EDS) webinar, May 2020.
    • S. Yu, “Compute-in-Memory with Emerging Nonvolatile-Memories: Challenges and Prospects”, Qualcomm, webinar, Mar. 2020.
    • S. Yu, “RRAM based Compute-in-Memory for Machine Learning Accelerator”, Peking University, Beijing, China, Jan. 2020.
    • S. Yu, “RRAM based compute-in-memory for Machine Learning Accelerator”, Tsinghua University, Beijing, China, Jan. 2020.
    • S. Yu, “Compute-in-Memory for AI: From Inference to Training”, TSMC reception at IEDM, San Francisco, CA, Dec. 2019.
    • S. Yu, “Compute-in-Memory with RRAM Technology: Challenges and Prospects”, TSMC Webinar, Nov. 2019.
    • S. Yu, “Recent Progresses of Compute-in-Memory for Machine Learning Accelerator”, IBM TJ Watson Research Center, Yorktown Heights, NY, Nov. 2019.
    • S. Yu, “Compute-in-Memory for Machine Learning Accelerator”, Distinguished Lecture at Rice University, Houston, TX, Oct. 2019.
    • S. Yu, “Neuro-Inspired Computing with Nanoelectronic Devices: Experimental Progresses and Modeling Opportunities”, Plenary Talk, IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Udine, Italy, Sep. 2019.
    • S. Yu, “Recent Progresses of Compute-in-Memory for Machine Learning Accelerator”, IBM Zurich Research Center, Switzerland, Sep. 2019.
    • S. Yu, “Design of Light-weight RRAM Based Hardware Security Primitives for IoT Devices”, SRC e-workshop, Aug. 2019.
    • S. Yu, “Compute-in-Memory with RRAM Technologies,” ASCENT Emerging Hardware for Bio-Inspired Computing Workshop, Notre Dame, IN, Aug. 2019.
    • S. Yu, “Emerging Non-Volatile Memory’s Applications in Neuro-Inspired Computing and Hardware Security,” Keynote Speech, IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Hangzhou, China, July 2019.
    • S. Yu, “Compute-in-Memory for Machine Learning Accelerator”, Zhejiang University, Hangzhou, China, Jul. 2019.
    • S. Yu, “Compute-in-Memory with SRAM and RRAM Technologies,” IEEE Custom Integrated Circuits Conference (CICC) Forum, Austin, TX, Apr. 2019.
    • S. Yu, “Neuro-Inspired Computing with Synaptic and Neuronal Devices”, Nano@Tech Seminar, Georgia Institute of Technology, Atlanta, GA, Apr. 2019.
    • S. Yu, J.-S. Seo, “XNOR-RRAM: In-Memory Computing for Binary Deep Neural Networks Using Monolithically-Integrated RRAM/CMOS Technology”, SRC e-workshop, Apr. 2019.
    • S. Yu, “Compute-in-Memory for Machine Learning Accelerator”, Shanghai Jiaotong University, Shanghai, China, Mar. 2019.
    • S. Yu, ““Neuro-Inspired Computing with Synaptic and Neuronal Devices”, University of Science and Technology of China, Hefei, China, Mar. 2019.
    • S. Yu, “Compute-in-Memory with SRAM Technologies,” IEEE Custom Integrated Circuits Conference (CICC) Forum, Austin, TX, Apr. 2019.
    • S. Yu, “Computing-in-Memory for Binary Neural Networks”, China Semiconductor Technology International Conference (CSTIC), Shanghai, China, Mar. 2019.
    • S. Yu, “Compute-in-Memory for Machine Learning Accelerator”, On Semiconductor, on-site visit, Atlanta, GA, Feb. 2019.
    • S. Yu, “Exploiting Hybrid Precision for Training and Inference in Deep Neural Network: a FeFET based Synaptic Weight Cell,” Future Chips Forum of Tsinghua University, Beijing, China, Dec. 2018.
    • S. Yu, “FeFET based Synaptic Device”, Tsinghua/Notre Dame Joint Workshop on Device to Application Benchmarking, Beijing, China, Dec. 2018.
    • S. Yu, “Device-to-System Evaluation Framework for Cognitive Microsystems”, IBM, Albany, NY, Nov. 2018.
    • S. Yu, “Neuro-Inspired Computing with Resistive Synaptic Devices”, UT Dallas, Dallas, TX, Oct. 2018.
    • S. Yu, “Requirement of Selector Device for Neuromorphic Computing”, 8th Stanford/IMEC RRAM Workshop, Stanford, CA, Oct. 2018.
    • S. Yu, “Device-to-System Evaluation Framework for Cognitive Microsystems”, Intel, Hillsboro, OR, Sep. 2018.
    • S. Yu, “Neuro-Inspired Computing with Resistive Synaptic Devices”, Applied Materials, Santa Clara, CA, Aug. 2018
    • S. Yu, “Compute-in-Memory Architectures for Neural Network Accelerators: From CMOS to Post-CMOS”, Samsung, Austin, TX, May 2018.
    • S. Yu, “Compute-in-Memory Architectures for Neural Network Accelerators: From CMOS to Post-CMOS”, ARM, San Jose, CA, Apr. 2018.
    • S. Yu, “Compute-in-Memory Architectures for Neural Network Accelerators: From CMOS to Post-CMOS”, Western Digital, Milpitas, CA, Apr. 2018.
    • S. Yu, “Reliability Effects of Resistive Synaptic Devices on Neuromorphic Computing System Performance”, IEEE VLSI Test Symposium, San Francisco, CA, Apr. 2018.
    • S. Yu, “Neuro-Inspired Computing with Resistive Synaptic Devices”, TSMC, Webinar, Mar. 2018.
    • S. Yu, “Compute-in-Memory Architectures for Neural Network Accelerators: From CMOS to Post-CMOS”, UC-Santa Barbara, Santa Barbara, CA, Feb. 2018.
    • S. Yu, “Neuro-Inspired Computing with Resistive Synaptic Devices”, Carnegie Mellon University, Pittsburgh, PA, Jan. 2018.
    • S. Yu, “Neuro-Inspired Computing with Resistive Synaptic Devices”, Georgia Institute of Technology, Atlanta, GA, Dec. 2017.
    • S. Yu, “Neuro-Inspired Computing with Emerging Non-Volatile Memory (NVM)”, Future Chips Forum of Tsinghua University, Beijing, China, Dec. 2017.
    • S. Yu, “Deep Learning with Emerging Non-Volatile Memory (NVM)”, GigaDevice, Beijing, China, Dec. 2017.
    • S. Yu, “Neuro-Inspired Computing with Emerging Non-Volatile Memory (NVM)”, Western Digital, San Jose, CA, Dec. 2017.
    • S. Yu, “Neuro-Inspired Computing with Emerging Non-Volatile Memory (NVM)”, Departmental ECE Colloquium, University of Minnesota, Minneapolis, MN, Nov. 2017.
    • S. Yu, “Neuro-Inspired Computing with Emerging Non-Volatile Memory (NVM)”, Nanoscience and Nanotechnology Seminar Series, University of South California, Los Angeles, CA, Nov. 2017.
    • S. Yu, “System-level Benchmark of Resistive Synaptic Device Characteristics for Neuro-inspired Computing,” ARO/UCSD workshop on Neuro-inspired Computing Using Nanoelectronic Devices, San Diego, CA, Oct. 2017.
    • S. Yu, “Neuro-Inspired Computing with Emerging Non-Volatile Memory (NVM)”, Army Research Laboratory (ARL), on-site visit, Tempe, AZ, Sep. 2017.
    • S. Yu, “System-level Benchmark of Resistive Synaptic Device Characteristics for Neuro-inspired Computing,” 7th Stanford/IMEC RRAM Workshop, Leuven, Belgium, Sep. 2017.
    • S. Yu, “Neuro-Inspired Computing with Emerging Non-Volatile Memory (NVM)”, IMEC, Leuven, Belgium, Sep. 2017.
    • S. Yu, “Neuro-Inspired Computing with Emerging Non-Volatile Memory (NVM)”, ShanghaiTech Workshop on Emerging Devices, Circuits and Systems, Shanghai, China, Jul. 2017.
    • S. Yu, “Neuro-Inspired Computing with Emerging Non-Volatile Memory (NVM)”, Computer Science Faculty Talk Series, Arizona State University, Tempe, AZ, Apr. 2017.
    • S. Yu, “Binary Neural Network and Its Implementation with 16 Mb RRAM Macro Chip”, 5th Neuro Inspired Computational Elements (NICE) Workshop, IBM Almaden, San Jose, CA, Mar. 2017.
    • S. Yu, “Resistive Switching Devices: From Memory to Neuro-Inspired Computing and Hardware Security”, Northwestern University, Evanston, IL, Feb. 2017.
    • S. Yu, “Resistive Random Access Memory (RRAM)’s Applications for Neuro-inspired Computing and Hardware Security”, University of Michigan, Ann Arbor, MI, Feb. 2017.
    • S. Yu, “Neuro-Inspired Computing with Emerging Non-Volatile Memory (NVM)”, Qualcomm, San Diego, CA, Jan. 2017.
    • S. Yu, “Recent Progress of Neuro-inspired Computing with Resistive Synaptic Devices”, Peking University, Beijing, China, Dec. 2016.
    • S. Yu, “Recent Progress of Neuro-inspired Computing with Resistive Synaptic Devices”, South University of Science and Technology of China, Shenzhen, China, Dec. 2016.
    • S. Yu, “Design and Experimental Characterization of RRAM based Physical Unclonable Function (PUF) for Hardware Security,” 6th Stanford/IMEC RRAM Workshop, Stanford, CA, Oct. 2016.
    • S. Yu, “Impact of Non-Ideal Resistive Synaptic Device Behaviors on Neuromorphic System Performances,” 13th U.S.-Korea Forum on Nanotechnology, Seoul, Korea, Sep. 2016.
    • S. Yu, “Scaling-up Resistive Synaptic Arrays for Neuro-inspired Computing: Challenges and Prospects,” Korea Institute of Science and Technology, Seoul, Korea, Sep. 2016.
    • S. Yu, “Scaling-up Resistive Synaptic Arrays for Neuro-inspired Architecture: Challenges and Prospect”, ESSDERC-ESSCIRC Workshop on Technology and Architectures Development for Brain Inspired Integrated Circuits, Lausanne, Switzerland, Sep. 2016.
    • S. Yu, “Scaling-up Synaptic Crossbar Array for Neuromorphic Computing: Challenges and Prospects,” IBM TJ Watson Research Center, Yorktown Heights, NY, Aug. 2016.
    • S. Yu, “Resistive Random Access Memory (RRAM)’s Applications for Neuro-inspired Computing and Hardware Security,” University of Massachusetts, Amherst, MA, Aug. 2016.
    • S. Yu, “Scaling-up Synaptic Crossbar Array for Neuromorphic Computing: Challenges and Prospects,” Air Force Research Laboratory, Rome, NY, July 2016.
    • S. Yu, “Scaling-up Resistive Synaptic Array for Neuromorphic Computing: Challenges and Prospects,” Cornell University, Ithaca, NY, July 2016.
    • S. Yu, “Resistive Random Access Memory (RRAM)’s Applications for Neuro-inspired Computing and Hardware Security,” Syracuse University, Syracuse, NY, July 2016.
    • S. Yu, “Exploring Variability of Emerging Nano-Devices for Hardware Security: A Case Study of RRAM based PUF,” International Workshop on Hardware Security, Tsinghua University, Beijing, China, June 2016.
    • S. Yu, “Exploring Variability of Emerging Nano-Devices for Hardware Security: A Case Study of RRAM based PUF,” Peking University, Beijing, China, June 2016.
    • S. Yu, “Neuro-inspired Computing using Resistive Memories”, Emerging Technologies on Communications, Microsystems, Optoelectronics, Sensors (ET-CMOS), Montreal, Canada, May 2016.
    • S. Yu, “Resistive Random Access Memory (RRAM)’s Applications for Neuro-inspired Computing and Hardware Security,” National Tsing-Hua University, Hsinchu, Taiwan, Apr. 2016.
    • S. Yu, “Resistive Random Access Memory (RRAM)’s Applications for Neuro-inspired Computing and Hardware Security,” National Chiao-Tung University, Hsinchu, Taiwan, Apr. 2016.
    • S. Yu, “Resistive Random Access Memory (RRAM)’s Applications for Neuro-inspired Computing and Hardware Security,” National Cheng-Kung University, Tainan, Taiwan, Apr. 2016.
    • S. Yu, “Neuro-inspired Computing using Resistive Memories,” HP Labs, Palo Alto, CA, Mar. 2016.
    • S. Yu, “Neuro-inspired Computing using Resistive Memories,” UC Berkeley, Berkeley, CA, Mar. 2016.
    • S. Yu, “Neuro-inspired Computing using Resistive Memories,” Stanford University, Stanford, CA, Mar. 2016.
    • S. Yu, “Resistive Random Access Memory (RRAM)’s Applications for Neuro-inspired Computing,” Tsinghua University, Beijing, China, Dec. 2015.
    • S. Yu, “Resistive Random Access Memory (RRAM)’s Applications for Neuro-inspired Computing,” Peking University, Beijing, China, Dec. 2015.
    • S. Yu, “Resistive Random Access Memory (RRAM)’s Applications for Neuro-inspired Computing and Hardware Security,” UT-Austin, TX, Nov. 2015.
    • S. Yu, “Resistive Memories for Neuro-Inspired Computing: A Holistic View from Devices to Architectures,” 5th Stanford/IMEC RRAM Workshop, Leuven, Belgium, Sep 2015.
    • S. Yu, “Resistive Random Access Memory (RRAM): Modeling, Radiation Harsh Environments, and Neuromorphic Applications,” Sandia National Laboratories, Albuquerque, NM, Aug. 2015.
    • S. Yu, “Resistive Random Access Memory (RRAM): Mechanism, Modeling, 3D Integration, Hardware Security, and Neuromorphic Applications,” Globalfoundries, San Jose, CA, June 2015.
    • S. Yu, “Resistive Random Access Memory (RRAM): Mechanism, Modeling, 3D Integration, Hardware Security, and Neuromorphic Applications,” IBM Almaden Research Center, San Jose, CA, June 2015.
    • S. Yu, “Resistive Random Access Memory (RRAM): Mechanism, Modeling, 3D Integration, Radiation Effects, and Neuromorphic Applications,” CEA-LETI, Grenoble, France, Mar 2015.
    • S. Yu, “Resistive Random Access Memory (RRAM): Modeling, 3D Integration and Neuromorphic Applications,” Samsung, San Jose, USA, Nov 2014.
    • S. Yu, “Resistive Random Access Memory (RRAM): A Tutorial,” Peking University, Beijing, China, May 2014.
    • S. Yu, “Resistive Random Access Memory (RRAM): Modeling, 3D Integration and Neuromorphic Applications,” Tsinghua University, Beijing, China, May 2014.
    • S. Yu, “Resistive Random Access Memory (RRAM): Modeling, 3D Integration and Neuromorphic Applications,” Institute of Microelectronics, Chinese Academy of Science, Beijing, China, May 2014.
    • S. Yu, “Brain-inspired computing with synaptic devices,” Connection One Seminar, Arizona State University, Tempe, AZ, USA, Oct. 2013.
    • S. Yu, “Resistive Switching Memory (RRAM): Modeling, Reliability Characterization and 3D Integration,” SanDisk, Milpitas, CA, Oct. 2013.
    • S. Yu, “Resistive Switching Memory (RRAM): Modeling, Reliability Characterization and 3D Integration,” Rambus, Sunnyvale, CA, Oct. 2013.
    • S. Yu, “Resistive Switching Memory (RRAM): Modeling, Reliability Characterization and 3D Integration,” Intermolecular, San Jose, CA, Oct. 2013.
    • S. Yu, “Brain-inspired computing with synaptic devices,” Penn. State University, University Park, PA, USA, Oct. 2013.
    • S. Yu, “Brain-inspired computing with synaptic devices,” University of Pittsburgh, Pittsburgh, PA, Oct. 2013.
    • S. Yu, “Brain-inspired computing with synaptic devices,” Telluride Neuromorphic Engineering Workshop, Telluride, CO, Jul. 2013.
    • S. Yu, “Emerging device technology for future computing paradigms,” Synopsys, Mountain View, CA, USA, May 2013.
    • S. Yu, “Emerging device technology for future computing paradigms,” Rohm Semiconductor, Santa Clara, CA, USA, Apr. 2013.
    • S. Yu, “Emerging device technology for future computing paradigms,” UCLA, Los Angeles, CA, USA, Apr. 2013.
    • S. Yu, “Emerging device technology for future computing paradigms,” Penn. State University, University Park, PA, USA, Mar. 2013.
    • “Emerging device technology for future computing paradigms,”, UC Berkeley, Berkeley, CA, USA, Mar. 2013.
    • S. Yu, “Emerging device technology for future computing paradigms,” Princeton University, Princeton, NJ, USA, Mar. 2013.
    • S. Yu, “Emerging device technology for future computing paradigms,” Arizona State University, Tempe, AZ, USA, Mar. 2013.
    • S. Yu, “Emerging device technology for future computing paradigms,” MIT, Cambridge, MA, USA, Feb. 2013.
    • S. Yu, “Emerging device technology for future computing paradigms,” Applied Materials,  Santa Clara, CA, USA, Feb. 2013.
    • S. Yu, “Emerging device technology for future computing paradigms,” UC Riverside, Riverside, CA, USA, Feb. 2013.
    • S. Yu, “Emerging device technology for future computing paradigms,” Altera, San Jose, CA, USA, Feb. 2013.
    • S. Yu, “Bio-inspired neuromorphic computing with solid-state synaptic devices,” Physical Sciences Colloquium of IBM TJ Watson Research Center, Yorktown Heights, NY, USA, Sep. 2012.
    • S. Yu, “Bio-inspired neuromorphic computing with solid-state synaptic devices,” IBM Research Workshop on Materials, Devices and Technologies for New Computation Paradigms, Zurich, Switzerland, Aug. 2012.
    • S. Yu, “Metal oxide resistive switching memory (RRAM): physical mechanism and device modeling,” Micron Technology, San Jose, CA, USA, Nov. 2011.

    Special Session/Workshop Organizer:

    • Special session on “Design Automation Benchmark Framework and Simulators for Hardware Accelerators”, IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) 2021.
    • ARO/UCSD workshop on “Neuro-inspired Computing Using Nanoelectronic Devices” 2017.
    • Tutorial on “Neuromorphic Computing with Emerging Synaptic Devices”, IEEE European Solid-State Device Research Conference (ESSDERC) 2017.
    • Symposium on “Materials, Devices and Architectures for Neuromorphic Engineering and Brain-Inspired Computing”, MRS Fall Meeting 2017.
    • Special session on “Device-Circuit-System Integration Using Emerging Transistors”, IEEE International Symposium on Circuits and Systems (ISCAS) 2016.
    • Special session on “Device-Circuit-System Integration Using Emerging Memory (Part-I and Part-II)”, IEEE International Symposium on Circuits and Systems (ISCAS) 2015.
    • Special session on “3D Resistive Devices and CMOS Integration”, IEEE International Symposium on Circuits and Systems (ISCAS) 2014.

    Paper Reviewer:

    • Science
    • Science Advances
    • Nature
    • Nature Materials
    • Nature Nanotechnology
    • Nature Electronics
    • Nano Letters
    • ACS Nano
    • Advanced Materials
    • Advanced Functional Materials
    • Advanced Electronic Materials
    • Nanoscale
    • Nanotechnology
    • Applied Physics Letters
    • Journal of Applied Physics
    • Proceedings of the IEEE
    • IEEE Electron Device Letters
    • IEEE Transactions on Electron Devices
    • IEEE Journal on Electron Devices Society
    • IEEE Transactions on Nanotechnology
    • IEEE Journal of Solid-State Circuits
    • IEEE Solid-State Circuits Letters
    • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
    • IEEE Transactions on Very-Large-Scale-Systems
    • IEEE Transactions on Circuits and Systems I: Regular Papers
    • IEEE Transactions on Circuits and Systems II: Express Briefs
    • IEEE Journal on Emerging and Selected Topics in Circuits and Systems
    • IEEE Transactions on Computers
    • IEEE Transactions on Architecture and Code Optimization
    • IEEE Transactions on Neural Networks and Learning Systems
    • IEEE Transactions on Information Forensics & Security
    • IEEE Transactions on Nuclear Science
    • IEEE Transactions on Device and Materials Reliability
    • IEEE Micro
    • IEEE Access
    • ACM Journal on Emerging Technologies in Computing Systems
    • IBM Journal of Research and Development
    • Journal of Physics D: Applied Physics
    • Semiconductor Science and Technology
    • Journal of Semiconductors
    • Journal of the Electrochemical Society
    • ECS Journal of Solid State Science and Technology
    • Electrochemical and Solid-State Letters
    • Thin Solid Films
    • Solid State Electronics
    • Journal of Vacuum Science and Technology: A
    • Applied Physics A
    • Journal of Computational Electronics
    • Scientific Report
    • Frontiers in Neuroscience

    Proposal Reviewer:

    • NSF Panel Review 2015, 2016, 2017, 2018, 2019, 2021
    • NSF Ad Hoc Review 2019, 2020, 2021
    • ARO Proposal 2016
    • AFOSR Proposal 2019
    • DOE Proposal 2020
    • Canadian Natural Sciences and Engineering Research Council (NSERC) Strategic Project Grants 2016
    • European Research Council (ERC) Consolidator Grants 2018; Advanced Grant 2020
    • Taiwan Ministry of Science and Technology (MOST) program 2019
    • King Abdullah University of Science and Technology (KAUST) program 2019
    • Singapore Agency for Science, Technology and Research (A*STAR) 2019, 2020
    • Singapore National Research Foundation (NRF) 2020
    • Swiss National Science Foundation (SNF) 2019
    • South Korean National Research Foundation (NRF) 2021