6 IEDM papers accepted

Our group has 3 papers accepted, and also has 3 collaborative papers with University of Notre Dame and Rochester Institute of Technology to be presented at IEDM 2020 virtual in Dec. 2020. This is a new record of IEDM papers of our group, congratulations to all the authors!

  1. X. Peng, W. Chakraborty, A. Kaul, M. S. Bakir, S. Datta, S. Yu, “Benchmarking monolithic 3D integration for compute-in-memory accelerators: overcoming ADC bottlenecks and maintaining scalability to 7nm or beyond,” IEEE International Electron Devices Meeting (IEDM) 2020, virtual.
  2. P. Wang, X. Peng, W. Chakraborty, A. I. Khan, S. Datta, S. Yu, “Cryogenic benchmarks of embedded memory technologies for recurrent neural network based quantum error correction,” IEEE International Electron Devices Meeting (IEDM) 2020, virtual.
  3. J. Hur, P. Wang, Z. Wang, G. Choe, N. Tasneem, A. I. Khan, S. Yu, “Interplay of switching characteristics, cycling endurance and multilevel retention of ferroelectric capacitor,” IEEE International Electron Devices Meeting (IEDM) 2020, virtual.
  4. S. Dutta, H. Ye, W. Chakraborty, Y.-C. Luo, M. San Jose, B. Grisafe, A. Khanna, I. Lightcap, S. Shinde, S. Yu, S. Datta, “Monolithic 3D integration of high endurance multi-bit ferroelectric FET for accelerating compute-in-memory,” IEEE International Electron Devices Meeting (IEDM) 2020, virtual.
  5. Z. Wang, M. M. Islam, P. Wang, S. Deng, S. Yu, A. I. Khan, K. Ni, “Depolarization field induced instability of polarization states in HfO2 based ferroelectric FET,” IEEE International Electron Devices Meeting (IEDM) 2020, virtual.
  6. A. Kaul, X. Peng, S. K. Raja, S. Yu, M. S. Bakir, “Thermal modeling of 3D polylithic integration and implications on BEOL RRAM performance, IEEE International Electron Devices Meeting (IEDM) 2020, virtual, invited.

Prof. Yu received DAC Under-40 Innovators Award

Prof. Yu received the ACM/IEEE Design Automation Conference (DAC) Under-40 Innovators Award in 2020 owing to his contribution to the pioneering research on benchmarking hardware accelerators for machine learning. See the news at

https://www.dac.com/media-center/dac-news/three-exceptional-innovators-selected-receive-design-automation-conference

https://www.ece.gatech.edu/news/636895/yu-chosen-dac-under-40-innovators-award

2 IEDM papers and 1 ISSCC paper accepted

Our group has 1 paper accepted, and also has 1 collaborative paper with Purdue University to be presented at IEDM 2019, at San Francisco, CA, in Dec. 2019.

X. Peng, S. Huang, Y. Luo, X. Sun, S. Yu, “DNN+NeuroSim: An end-to-end benchmarking framework for compute-in-memory accelerators with versatile device technologies,” IEEE International Electron Devices Meeting (IEDM) 2019, San Francisco, USA.

M. Si, Y. Luo, W. Chung, H. Bae, D. Zheng, J. Li, J. Qin, G. Qiu, S. Yu, P. D. Ye, “A novel scalable energy-efficient synaptic device: crossbar ferroelectric semiconductor junction,” IEEE International Electron Devices Meeting (IEDM) 2019, San Francisco, USA.

Our group has one collaborative paper with National Tsinghua University (Taiwan) to be presented at ISSCC 2020, at San Francisco, CA, in Feb. 2020.

J-W. Su, X. Si, Y-C. Chou, T-W. Chang, W-H. Huang, Y-N. Tu, R. Liu, P-J. Lu, T-W. Liu, J-H. Wang, Z. Zhang, H. Jiang, S. Huang, S. Yu, K-T. Tang, C-C. Hsieh, R-S. Liu, S-H. Li, S-S. Sheu, H-Y. Lee, S-C. Chang, M-F. Chang, “A 28nm 64Kb inference-training two-way transpose multibit 6T SRAM coumputing-in-memory macro for AI edge chips” IEEE International Solid-State Circuits Conference (ISSCC) 2020, San Francisco, USA.