Our group has 1 paper accepted, and also has 1 collaborative paper with Purdue University to be presented at IEDM 2019, at San Francisco, CA, in Dec. 2019.
X. Peng, S. Huang, Y. Luo, X. Sun, S. Yu, “DNN+NeuroSim: An end-to-end benchmarking framework for compute-in-memory accelerators with versatile device technologies,” IEEE International Electron Devices Meeting (IEDM) 2019, San Francisco, USA.
M. Si, Y. Luo, W. Chung, H. Bae, D. Zheng, J. Li, J. Qin, G. Qiu, S. Yu, P. D. Ye, “A novel scalable energy-efficient synaptic device: crossbar ferroelectric semiconductor junction,” IEEE International Electron Devices Meeting (IEDM) 2019, San Francisco, USA.
Our group has one collaborative paper with National Tsinghua University (Taiwan) to be presented at ISSCC 2020, at San Francisco, CA, in Feb. 2020.
J-W. Su, X. Si, Y-C. Chou, T-W. Chang, W-H. Huang, Y-N. Tu, R. Liu, P-J. Lu, T-W. Liu, J-H. Wang, Z. Zhang, H. Jiang, S. Huang, S. Yu, K-T. Tang, C-C. Hsieh, R-S. Liu, S-H. Li, S-S. Sheu, H-Y. Lee, S-C. Chang, M-F. Chang, “A 28nm 64Kb inference-training two-way transpose multibit 6T SRAM coumputing-in-memory macro for AI edge chips” IEEE International Solid-State Circuits Conference (ISSCC) 2020, San Francisco, USA.