Publication

Total Citations: >30,000  H-index: 82 (according to Google Scholar)

Journal papers         Conference papers

Book/Book chapters:

  1. H. Jiang, S. Huang, S. Yu, “Compute-in-memory architecture”, Handbook of Computer Architecture, A. Chattopadhyay (Ed.), Publisher: Springer, 2023.
  2. S. Yu, Semiconductor Memory Devices and Circuits, Publisher: CRC Press/Taylor & Francis, 2022. [Link]
  3. J.-S. Seo, S. Yu, “Neuro-inspired computing and neuromorphic processors for biomedical circuits and systems,” Selected Topics in Biomedical Circuits and Systems, River Publishers Series in Circuits and Systems, 2021.
  4. S. Yu, R. Liu, X. Sun, H. Wu, Y. Pang, B. Gao, H. Qian, A. Chen, “RRAM based hardware security primitives,” Security Opportunities by Nano Devices and Emerging Technologies, M. Tehranipoor, D. Forte, G. Rose, S. Bhunia (Eds.), Publisher: CRC Press/Taylor & Francis, 2020.
  5. S. Yu (Editor), Neuro-inspired Computing Using Resistive Synaptic Devices, Publisher: Springer, 2017. [Link]
  6. S. Yu, Resistive Random Access Memory (RRAM): From Devices to Array Architectures, Synthesis Lectures on Emerging Engineering Technologies 2 (5), 1-79, Publisher: Morgan & Claypool, 2016. [Link]
  7. R. Waser, D. Ielmini, H. Akinaga, H. Shima, H.-S. P. Wong, J. J. Yang, and S. Yu, “Introduction to nanoionic elements for information technology,” Resistive Switching: From Fundamentals of Nanoionic Redox Processes to Memristive Device Applications, D. Ielmini, R. Waser (Eds.), Publisher: Wiley, 2016.
  8. S. Yu, B. Lee, and H.-S. P. Wong, “Metal oxide resistive switching memory,” Functional Metal Oxide Nanostructures, J. Wu, J. Cao, W.-Q. Han, A. Janotti, H.-C. Kim, (Eds.), Publisher: Springer, 2011.

Journal papers:

  1. S. Yu, T.-H. Kim, “Semiconductor memory technologies: State-of-the-art and future trends,” IEEE Computer Magazine, vol. 57, no. 4, pp. 150-154, 2024, invited review.
  2. O. Phadke, S. G. Kirtania, D. Chakraborty, S. Datta, S. Yu, “Suppressed capacitive coupling in 2 transistor gain cell with oxide channel and split gate,” IEEE Trans. Electron Devices, vol. 71, no. 11, pp. 6749-6755, 2024.
  3. A. Lu, J. Lee, T.-H. Kim, M. Karim, R. Park, H. Simka, S. Yu, “High-speed emerging memories for AI hardware accelerators,” Nature Reviews Electrical Engineering, vol. 1, pp. 24-34, 2024, invited review.
  4. J. Lee, A. Lu, W. Li, S. Yu, “NeuroSim V1.4: Extending technology support for digital compute-in-memory towards 1nm node,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 71, no. 4, pp. 1733-1744, 2024.
  5. Y. Luo, S. Yu, “H3D-Transformer: A heterogeneous 3D (H3D) computing platform for transformer model acceleration on edge devices,” ACM Transactions on Design Automation of Electronic Systems, vol. 29, no. 3, article 47, 2024.
  6. P.-K. Hsu, V. Garg, A. Lu, S. Yu, “A heterogeneous platform for 3D NAND-based in-memory hyperdimensional computing engine for genome sequencing applications,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 71, no. 4, pp. 1628-1637, 2024.
  7. C.-K. Kim, O. Phadke, T.-H. Kim, M.-S. Kim, J.-M. Yu, M.-S. Yoo, Y.-K. Choi, S. Yu, “Capacitive synaptor with overturned charge injection for compute-in-memory,” IEEE Electron Device Lett., vol. 45, no. 5, pp. 929-932, 2024, editor’s pick.
  8. C.-K. Kim, J. Read, M. Shon, T.-H. Kim, M.-S. Kim, J.-M. Yu, M.-S. Yoo, Y.-K. Choi, S. Yu, “Capacitive synaptor with gate surrounding semiconductor pillar structure and overturned charge injection for compute-in-memory,” Advanced Intelligent Systems, accepted.
  9. G. Choe, J. Kwak, S. Yu, “Machine learning-assisted compact modeling of W-doped indium oxide channel transistor for back-end-of-line applications,” IEEE Trans. Electron Devices, vol. 71, no. 1, pp. 231-238, 2024.
  10. Y.-C. Luo, A. Lu, Y. Luo, S.-C. Chang, U. Avci, S. Yu, “Endurance-aware compiler for 3D stackable FeRAM as global buffer in TPU-like architecture,” IEEE Trans. VLSI Systems, vol. 32, no. 9, pp. 1696-1703, 2024.
  11. Y.-C. Luo, A. Lu, J. Sharda, M. Scherer, J. T. Gomez, S. S. Sarwar, Z. Li, R. F. Pinkham, B. De Salvo, S. Yu, “Thermally-constrained co-design of heterogeneous 3D integration of compute-in-memory, digital ML accelerator, and RISC-V cores for mixed ML and non-ML workloads,” IEEE Trans. VLSI Systems, vol. 32, no. 9, pp. 1718-1725, 2024.
  12. Y.-C. Luo, A. Khanna, B. Grisafe, J. Sun, S. Dutta, L. E. Noskin, C. Adamo, A. B. Mei, R. K. Ghosh, M. Colletta, M. E. Holtz, V. Gambin, L. F. Kourkoutis, S. Yu, D. G. Schlom, S. Datta, “Correlated oxide selector for cross-point embedded non-volatile memory,” IEEE Trans. Electron Devices, vol. 71, no. 1, pp. 916-921, 2024.
  13. Y. Luo, J. Vanderhaegen, O. Rybakov, M. Kraemer, N. Warren, S. Yu, “A FeFET-based ADC offset robust compute-in-memory architecture for streaming keyword spotting (KWS),” IEEE Transactions on Emerging Topics in Computing, vol. 12, no. 1, pp. 23-34, 2024.
  14. S. Woo, K. A. Aabrar, S. Datta, S. Yu, “Analyzing total-ionizing-dose induced memory window degradation in ferroelectric FinFET,” IEEE Transactions on Device and Materials Reliability, vol. 24, no. 1, pp. 84-88, 2024.
  15. S. Woo, G. Choe, A. I. Khan, S. Datta, S. Yu, “Design of superlattice ferroelectric-metal field-effect transistor for triple-level cell 3D NAND Flash,” Microelectronic Engineering, vol. 295, 112276, 2025.
  16. J. Sharda, M. Manley, A. Kaul, W. Li, M. S. Bakir, S. Yu, “Design and thermal analysis of 2.5D and 3D integrated system of a CMOS image sensor and a sparsity-aware accelerator for autonomous driving,” IEEE Journal of the Electron Devices Society, vol. 12, pp. 426-432, 2024.
  17. J. Kwak, G. Choe, S. Yu, “Design-technology co-optimization for stacked nanosheet oxide channel transistors in monolithic 3D integrated circuit design,” IEEE Transactions on Nanotechnology, vol. 23, pp. 622-628, 2024.
  18. O. Phadke, T.-H. Kim, Y.-C. Luo, S. Yu, “Ferroelectric nonvolatile capacitive synapse for charge domain compute-in-memory,” ECS Transactions, vol. 113, p. 3, 2024, invited.
  19. S. Deng, J. Kwak, J. Lee, D. Chakraborty, J. Shin, O. Phadke, S. G. Kirtania, C. Zhang, K. A. Aabrar, S. Yu, S. Datta, “Monolithic switched-capacitor DC-DC voltage converters using BEOL-compatible oxide power transistors and superlattice MIM capacitors,” IEEE Trans. Electron Devices, accepted.
  20. C. Park, P. V. Ravindran, D. Das, P. G. Ravikumar, C. Zhang, N. Afroze, L. Fernandes, Y.-H. Kuo, J. Hur, H. Chen, M. Tian, W. Chern, S. Yu, A. I. Khan, “Plasma-enhanced atomic layer deposition based ferroelectric field-effect transistors,” IEEE Journal of the Electron Devices Society, vol. 12, pp. 569-572, 2024.
  21. L. Fernandes, P. V. Ravindran, T. Song, D. Das, C. Park, N. Afroze, M. Tian, H. Chen, W. Chern, S. Yu, S. Datta, A. I. Khan, “Material choices for tunnel dielectric layer and gate blocking layer for ferroelectric NAND applications,” IEEE Electron Device Lett., vol. 45, no. 10, pp. 1776-1779, 2024.
  22. P. Venkatesan, C. Park, T. Song, L. Fernandes, D. Das, N. Afroze, P. G. Ravikumar, M. Tian, H. Chen, W. Chern, K. Kim, J. Woo, S. Lim, K. Kim, W. Kim, D. Ha, S. Mahapatra, S. Yu, S. Datta, A. I. Khan, “Disturb and its mitigation in ferroelectric field-effect transistors with large memory window for NAND Flash applications,” IEEE Electron Device Lett., accepted.
  23. I. Yeo, W. He, Y.-C. Luo, S. Yu, J.-S. Seo, “A dynamic power-only compute-in-memory macro with power-of-two nonlinear SAR ADC for non-volatile ferroelectric capacitive crossbar array,” IEEE Solid-State Circuits Letters, vol. 7, pp. 70-73, 2024.
  24. X. Yang, Z. Wang, X. S. Hu, C. H. Kim, S. Yu, M. Pajic, R. Manohar, Y. Chen, H. Li, “Neuro-symbolic computing: advancements and challenges in hardware-software co-design,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 3, pp. 1683-1689, 2024.
  25. M. Passlack, N. Tasneem, C. Park, P. V. Ravindran, H. Chen, D. Das, S. Yu, E. Chen, J.-F. Wang, C.-S. Chang, Y.-M. Lin, I. Radu, A. I. Khan, “The origin of memory window closure with bipolar stress cycling in silicon ferroelectric field-effect-transistors,” J. Appl. Phys., vol. 135, no. 13, 134501, 2024.
  26. S. Yu, Y.-C. Luo, T.-H. Kim, O. Phadke, “Non-volatile capacitive synapse: Device candidates for charge domain compute-in-memory,” IEEE Electron Devices Magazine, vol. 1, no. 2, pp. 23-32, 2023, invited review.
  27. T.-H. Kim, O. Phadke, Y.-C. Luo, H. Mulaosmanovic, J. Mueller, S. Duenkel, S. Beyer, A. I. Khan, S. Datta, S. Yu, “Tunable non-volatile gate-to-source/drain capacitance of FeFET for capacitive synapse,” IEEE Electron Device Lett., vol. 44, no. 10, pp. 1628-1631, 2023.
  28. J. Sharda, W. Li, Q. Wu, S. Chang, S. Yu, “Temporal frame filtering for autonomous driving using 3D-stacked global shutter CIS with IWO buffer memory and near-pixel compute,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 5, pp. 2074-2084, 2023.
  29. H. Jiang, S. Huang, W. Li, S. Yu, “ENNA: An efficient neural network accelerator design based on ADC-free compute-in-memory subarrays,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 1, pp. 353-363, 2023.
  30. G. Choe, P. V. Ravindran, J. Hur, M. Lederer, A. Reck, A. I. Khan, S. Yu, “Machine learning assisted statistical variation analysis of ferroelectric transistor: from experimental metrology to adaptive modeling,” IEEE Trans. Electron Devices, vol. 70, no. 4, pp. 2015-2020, 2023.
  31. J. Hur, D. S. Kang, D.-I. Moon, J.-M. Yu, Y.-K. Choi, S. Yu, “Cryogenic storage memory with high-speed, low-power, and long-retention performance,” Advanced Electronic Materials, vol. 9, no. 6, 2201299, 2023.
  32. A. Lu, J. Hur, Y.-C. Luo, H. Li, D. E. Nikonov, I. Young, Y.-K. Choi, S. Yu, “Scalable in-memory clustered annealer with temporal noise of charge trap transistor for large scale travelling salesman problems,” IEEE J. Emerg. Sel. Topics Circuits Syst. (JETCAS), vol. 13, no. 1, pp. 422-435, 2023.
  33. S. Huang, H. Jiang, S. Yu, “Hardware-aware quantization/mapping strategies for compute-in-memory accelerators,” ACM Transactions on Design Automation of Electronic Systems, vol. 28, no. 3, article 34, 2023.
  34. W. Li, M. Manley, J. Read, A. Kaul, M. S. Bakir, S. Yu, “H3DAtten: Heterogeneous 3D integrated hybrid analog and digital compute-in-memory accelerator for vision transformer self-attention,” IEEE Trans. VLSI Systems, vol. 31, no. 10, pp. 1592-1602, 2023.
  35. A. Kaul, Y. Luo, X. Peng, M. Manley, Y.-C. Luo, S. Yu, M. S. Bakir, “3D heterogeneous integration of RRAM-based compute-in-memory: impact of integration parameters on inference accuracy,” IEEE Trans. Electron Devices, vol. 70, no. 2, pp. 485-492, 2023.
  36. T. Xie, S. Yu, S. Li, “A high-parallelism RRAM-based compute-in-memory macro with intrinsic impedance boosting and in-ADC computing,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JXCDC), vol. 9, no. 1, pp. 38-46, 2023.
  37. C. Park, H. Kashyap, D. Das, J. Hur, N. Tasneem, S. Lombardo, N. Afroze, W. Chern, A. C. Kummel, S. Yu, A. I. Khan, “Interfacial oxide layer scavenging in ferroelectric Hf0.5Zr0.5O2-based MOS structures with Ge channel for reduced write voltages,” IEEE Trans. Electron Devices, vol. 70, no. 8, pp. 4479-4483, 2023.
  38. D. Das, P. V. Ravindran, C. Park, N. Tasneem, Z. Wang, H. Chen, W. Chern, S. Yu, S. Datta, A. I. Khan, “A Ge-channel ferroelectric field effect transistor with logic-compatible write voltage,” IEEE Electron Device Lett., vol. 44, no. 2, pp. 257-260. 2023.
  39. N. Tasneem, Z. Wang, H. Chen, S. Yu, W. Chern, A. I. Khan, “Immediate read-after-write capability in p-type ferroelectric field-effect transistors and its evolution with fatigue cycling,” IEEE Transactions on Device and Materials Reliability, vol. 23, no. 1, pp. 142-146, 2023.
  40. S. Mukherjee, J. Bizindavyi, S. Clima, M. I. Popovici, X. Piao, K. Katcko, F. Cathoor, S. Yu, V. V. Afanasev, J. Van Houdt, “Capacitive memory window with nondestructive read in ferroelectric capacitors,” IEEE Electron Device Lett., vol. 44, no. 7, pp. 1092-1095, 2023.
  41. W. Li, X. Sun, S. Huang, H. Jiang, S. Yu, “A 40nm MLC-RRAM compute-in-memory macro with sparsity control, on-chip write-verify, and temperature-independent ADC references,” IEEE Journal of Solid State Circuits, vol. 57, no. 9, pp. 2868-2877, 2022.
  42. W. Li, J. Read, H. Jiang, S. Yu, “MAC-ECC: In-situ error correction and its design methodology for reliable NVM-based compute-in-memory inference engine,” IEEE J. Emerg. Sel. Topics Circuits Syst. (JETCAS), vol. 12, no. 4, pp. 835-845, 2022.
  43. J. Hur, Y.-C. Luo, T.-H. Wang, A. Lu, S. Li, A. I. Khan, S. Yu, “Non-volatile capacitive crossbar array for in-memory computing,” Advanced Intelligent Systems, vol. 4, 2100258, 2022.
  44. Y. Luo, Y.-C. Luo, S. Yu, “A Ferroelectric-based volatile/non-volatile dual-mode buffer memory for deep neural network accelerators,” IEEE Transactions on Computers, vol. 71, no. 9, pp. 2088-2101, 2022.
  45. A. Lu, Y. Luo, S. Yu, “An algorithm-hardware co-design for Bayesian neural network utilizing SOT-MRAM’s inherent stochasticity,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JXCDC), vol. 8, no. 1, pp. 27-34, 2022.
  46. W. Shim, S. Yu, “GP3D: 3D NAND based in-memory graph processing accelerator,” IEEE J. Emerg. Sel. Topics Circuits Syst. (JETCAS), vol. 12, no. 2, pp. 500-507, 2022.
  47. Y. Luo, S. Dutta, A. Kaul, S.-K. Lim, M. Bakir, S. Datta, S. Yu, “A compute-in-memory hardware accelerator design with back-end-of-line (BEOL) transistor based reconfigurable interconnect,” IEEE J. Emerg. Sel. Topics Circuits Syst. (JETCAS), vol. 12, no. 2, pp. 445-457, 2022.
  48. Y.-C. Luo, J. Hur, Z. Wang, W. Shim, A. I. Khan, S. Yu, “A technology path for scaling embedded FeRAM to 28nm and beyond with 2T1C structure,” IEEE Trans. Electron Devices, vol. 69, no. 1, pp. 109-114, 2022.
  49. J. Hur, C. Park, G. Choe, P. V. Ravindran, A. I. Khan, S. Yu, “Characterizing HfO2-based ferroelectric tunnel junction in cryogenic temperature,” IEEE Trans. Electron Devices, vol. 69, no. 10, pp. 5948-5951, 2022.
  50. Y. Luo, P. Wang, S. Yu, “Accelerating on-chip training with ferroelectric-based hybrid precision synapse,” ACM Journal on Emerging Technologies in Computing, vol. 18, no. 2, p. 35, 2022.
  51. H. Jiang, W. Li, S. Huang, S. Cosemans, F. Catthoor, S. Yu, “Analog-to-digital converter design exploration for compute-in-memory accelerators,” IEEE Design & Test, vol. 39, no. 2, pp, 48-55, 2022.
  52. S. Huang, X. Sun, X. Peng, H. Jiang, S. Yu, “Achieving high in-situ training accuracy and energy efficiency with analog non-volatile synaptic devices,” ACM Transactions on Design Automation of Electronic Systems, vol. 27, no. 4, article 37, 2022.
  53. Y.-C. Luo, A. Lu, J. Hur, S. Li, S. Yu, “Design and optimization of non-volatile capacitive crossbar array for in-memory computing,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 3, pp. 784-788, 2022.
  54. G. Choe, A. Lu, S. Yu, “3D AND-type ferroelectric transistors for compute-in-memory and the variability analysis,” IEEE Electron Device Lett., vol. 43, no. 2, pp. 304-307, 2022, Editor’s Pick.
  55. G. Choe, S. Yu, “Impact of polarization variation on ferroelectric field-effect transistor and compute-in-memory,” ECS Transaction, vol. 109, no. 4, p.73, 2022, invited..
  56. D. S. Kang, S. Yu, “Cryo-CMOS design-technology co-optimization of low noise amplifier for silicon qubit readout,” Microelectronic Engineering, vol. 262, 111837, 2022.
  57. D. S. Kang, S. Yu, “Time-based compute-in-memory for cryogenic neural network with successive-approximation register time-to-digital converter”, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JXCDC), vol. 8, no. 2, pp. 128-133, 2022.
  58. K. A. Aabrar, S. G. Kirtania, F.-X. Liang, J. Gomez, M. San Jose, Y. Luo, H. Ye, S. Dutta, P. G. Ravikumar, P. V. Ravindran, A. I. Khan, S. Yu, S. Datta, “BEOL compatible superlattice FeFET analog synapse with improved linearity and symmetry of weight update,” IEEE Trans. Electron Devices, vol. 69, no. 4, pp. 2094-2100, 2022.
  59. N. Tasneem, M. M. Islam, Z. Wang, Z. Zhao, N. Upadhyay, S. F. Lombardo, H. Chen, J. Hur, D. Triyoso, S. Consiglio, K. Tapily, R. Clark, G. Leusink, S. Kurinec, S. Datta, S. Yu, K. Ni, M. Passlack, W. Chern, A. I. Khan, “Efficiency of ferroelectric field-effect transistors: An experimental study,” IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1568-1574, 2022.
  60. Z. Wang, N. Tasneem, M. M. Islam, H. Chen, J. Hur, W. Chern, S. Yu, A. I. Khan, “An empirical compact model for ferroelectric field-effect transistor calibrated to experimental data,” IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1519-1523, 2022.
  61. M. Hoffmann, Z. Wang, N. Tasneem, A. Zubair, P. V. Ravindran, M. Tian, A. Gaskell, D. Triyoso, S. Consiglio, K. Tapily, R. Clark, J. Hur, S. S. K. Pentapati, S.-K. Lim, M. Dopita, S. Yu, W. Chern, J. Kacher, S. E. Reyes-Lillo, D. Antoniadis, J. Ravichandran, S. Slesazeck, T. Mikolajick, A. I. Khan, “Antiferroelectric negative capacitance from a structural phase transition in zirconia,” Nature Communications, vol. 13, 1228, 2022.
  62. K. Chae, S. F. Lombardo, N. Tasneem, M. Tian, H. Kumarasubramanian, J. Hur, W. Chern, S. Yu, C. Richter, P. D. Lomenzo, M. Hoffmann, U. Schroeder, D. Triyoso, S. Consiglio, K. Tapily, R. Clark, G. Leusink, N. Bassiri-Gharb, P. Bandaru, J. Ravichandran, A. Kummel, K. Cho, J. Kacher, A. I. Khan, “Local epitaxial templating effects in ferroelectric and antiferroelectric ZrO2,” ACS Applied Materials & Interfaces, vol. 14, no. 32, pp. 36771-36780, 2022.
  63. N. Tasneem, H. Kashyap, K. Chae, C. Park, P.-C. Lee, S. Lombardo, N. Afroze, M. Tian, H. Kumarasubramanian, J. Hur, H. Chen, W. Chern, S. Yu, P. Bandaru, J. Ravichandran, K. Cho, J. Kacher, A. Kummel, A. I. Khan, “Remote oxygen scavenging of the interfacial oxide layer in ferroelectric hafnium-zirconium oxide-based metal-oxide-semiconductor structures”, ACS Applied Materials & Interfaces, vol. 14, no. 38, pp. 43897-43906, 2022.
  64. S. Dash, Y. Luo, A. Lu, S. Yu, S. Mukhopadhyay, “Robust processing-in-memory with multi-bit ReRAM using Hessian-driven mixed-precision computation,” IEEE Trans. CAD, vol. 41, no. 4, pp. 1006-1019, 2022.
  65. J. Meng, W. Shim, L. Yang, I. Yeo, D. Fan, S. Yu, J.-S. Seo, “Temperature-resilient RRAM-based in-memory computing for DNN inference,” IEEE Micro, vol. 42, no. 1, pp. 89-98, 2022.
  66. J.-W. Su, X. Si, Y.-C. Chou, T.-W. Chang, W.-H. Huang, Y.-N. Tu, R. Liu, P.-J. Lu, T.-W. Liu, J.-H. Wang, Y.-L. Chung, J.-S. Ren, H. Jiang, S. Huang, S.-H. Li, S.-S. Sheu, C.-I. Wu, C.-C. Lo, R.-S. Liu, C.-C. Hsieh, K.-T. Tang, S. Yu, M.-F. Chang, “Two-way transpose multibit 6T SRAM computing-in-memory macro for inference-training AI edge chips,” IEEE Journal of Solid-State Circuits, vol. 57, no. 2, pp. 609-624, 2022.
  67. S. K. Cherupally, J. Meng, A. Rakin, S. Yin, I. Yeo, S. Yu, D. Fan, J.-S. Seo, “Improving the accuracy and robustness of RRAM-based in-memory computing against RRAM hardware noise and adversarial attacks,” Semicond. Sci. Technol., vol. 37, 034001, 2022.
  68. S. Yu, H. Jiang, S. Huang, X. Peng, A. Lu, “Compute-in-memory chips for deep learning: recent trends and prospects”, IEEE Circuits and Systems Magazine, vol. 21, no. 3, pp. 31-56, 2021, invited review. [Link]
  69. S. Yu, W. Shim, X. Peng, Y. Luo, “RRAM for compute-in-memory: from inference to training,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 7, pp. 2753-2765, 2021, invited review. [Link]
  70. S. Yu, J. Hur, Y.-C. Luo, W. Shim, G. Choe, P. Wang, “Ferroelectric HfO2-based synaptic devices: recent trends and prospects,” Semicond. Sci. Technol., vol. 36, 104001, 2021, invited review. [Link]
  71. W. Shim, S. Yu, “Technological design of 3D NAND based compute-in-memory architecture for GB-scale deep neural network,” IEEE Electron Device Lett., vol. 42, no. 2, pp. 160-163, 2021.
  72. J. Hur, Y.-C. Luo, N. Tasneem, A. I. Khan, S. Yu, “Ferroelectric hafnium zirconium oxide compatible with back-end-of-line process,” IEEE Trans. Electron Devices, vol. 68, no. 7, pp. 3176-3180, 2021.
  73. X. Peng, A. Kaul, M. S. Bakir, S. Yu, “Heterogeneous 3D integration of multi-tier compute-in-memory accelerators: An electrical-thermal co-design,” IEEE Trans. Electron Devices, vol. 68, no. 11, 5598-5605, 2021.
  74. X. Peng, S. Huang, H. Jiang, A. Lu, S. Yu, “DNN+NeuroSim V2.0: An end-to-end benchmarking framework for compute-in-memory accelerators for on-chip training,” IEEE Trans. CAD, vol. 40, no. 11, pp. 2306-2319, 2021.
  75. A. Lu, X. Peng, W. Li, H. Jiang, S. Yu, “NeuroSim simulator for compute-in-memory hardware accelerator: validation and benchmark,” Frontiers in Artificial Intelligence, vol. 4, 659060, 2021.
  76. Y. Luo, S. Yu, “AILC: Accelerate on-chip incremental learning with compute-in-memory technology,” IEEE Transactions on Computers, vol. 70, no. 8, pp. 1225-1238, 2021, Feature Paper of the Month.
  77. A. Lu, X. Peng, Y. Luo, S. Huang, S. Yu, “A runtime reconfigurable design of compute-in-memory based hardware accelerator for deep learning inference,” ACM Transactions on Design Automation of Electronic Systems, vol. 26, no. 6, p. 45, 2021.
  78. S. Huang, H. Jiang, X. Peng, W. Li, S. Yu, “Secure XOR-CIM engine: Compute-in-memory SRAM architecture with embedded XOR encryption,” IEEE Trans. VLSI Systems, vol. 29, no. 12, pp. 2027-2039, 2021.
  79. J. Hur, Y.-C. Luo, Z. Wang, S. Lombardo, A. I. Khan, S. Yu, “Characterizing ferroelectric properties of Hf0.5Zr0.5O2 from deep-cryogenic temperature (4 K) to 400 K,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JXCDC), vol. 7, no. 2, pp. 168-174, 2021.
  80.  J. Hur, P. Wang, N. Tasneem, Z. Wang, A. I. Khan, S. Yu, “Exploring Argon plasma effect on ferroelectric Hf0.5Zr0.5O2 thin film atomic layer deposition,” Journal of Materials Research, vol. 36, pp. 1206-1213, 2021.
  81. W. Shim, S. Yu, “Ferroelectric field effect transistor based 3D NAND architecture for energy efficient on-chip training accelerator,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JXCDC), vol. 7, no. 1, pp. 1-9, 2021.
  82. W. Shim, S. Yu, “System-technology co-design of 3D NAND Flash based compute-in-memory inference engine,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JXCDC), vol. 7, no.1, pp. 61-69, 2021.
  83. Y.-C. Luo, J. Hur, S. Yu, “Ferroelectric tunnel junction based crossbar array design for neuro-inspired computing,” IEEE Trans. Nanotechnol., vol. 20, pp. 243-247, 2021, best paper award.
  84. G. Choe, W. Shim, P. Wang, J. Hur, A. I. Khan, S. Yu, “Impact of random phase distribution in ferroelectric transistors based 3D NAND architecture on in-memory computing,” IEEE Trans. Electron Devices, vol. 68, no. 5, pp. 2543-2548, 2021.
  85. G. Choe, S. Yu, “Variability study of ferroelectric field-effect transistors towards 7nm technology node,” IEEE Journal of the Electron Devices Society, vol. 9, pp. 1131-1136, 2021.
  86. G. Choe, S. Yu, “Multigate ferroelectric transistor design towards 3nm technology node,” IEEE Trans. Electron Devices, vol. 68, no. 11, pp. 5908-5911, 2021.
  87. Z. Wang, J. Hur, N. Tasneem, W. Chern, S. Yu, A. I. Khan, “Extraction of Preisach model parameters for fluorite-structure ferroelectrics and antiferroelectrics,” Scientific Reports, vol. 11, p. 12474, 2021.
  88. J. Noh, H. Bae, J. Li, Y. Luo, Y. Qu, T. J. Park, M. Si, X. Chen, A. R. Charnas, W. Chung, X. Peng, S. Ramanathan, S. Yu, P. D. Ye, “First experimental demonstration of robust HZO/β-Ga2O3 ferroelectric field-effect transistors as synaptic devices for artificial intelligence applications in a high-temperature environment,” IEEE Trans. Electron Devices, vol. 68, no. 5, pp. 2515-2521, 2021.
  89. G. Murali, X. Sun, S. Yu, S.-K. Lim, “Heterogeneous mixed-signal monolithic 3D in-memory computing using resistive RAM,” IEEE Trans. VLSI Systems, vol. 29, no. 2, pp. 386-396, 2021.
  90. J. Meng, L. Yang, X. Peng, S. Yu, D. Fan, J.-S. Seo, “Structured pruning of RRAM crossbars for efficient in-memory computing acceleration of deep neural networks,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no, 5, pp. 1576-1580, 2021.
  91. B. Kang, A. Lu, Y. Long, D. Kim, S. Yu, S. Mukhopadhyay, “Genetic algorithm based energy-aware CNN quantization for processing-in-memory architecture,” IEEE J. Emerg. Sel. Topics Circuits Syst. (JETCAS), vol. 11, no. 4, pp. 649-662, 2021.
  92. S. F. Lombardo, M. Tian, K. Chae, J. Hur, N. Tasneem, S. Yu, K. Cho, A. C. Kummel, J. Kacher, A. I. Khan, “Local epitaxial-like templating effects and grain size distribution in atomic layer deposited Hf0.5Zr0.5O2 thin film ferroelectric capacitors,” Appl. Phys. Lett., vol. 119, 092901, 2021.
  93. N. Tasneem, P. V. Ravindran, Z. Wang, J. Gomez, J. Hur, S. Yu, S. Datta, A. I. Khan, “Differential charge boost in hysteretic ferroelectric-dielectric heterostructure capacitors at steady state,” Appl. Phys. Lett., vol. 118, 122901, 2021.
  94. N. Tasneem, M. M. Islam, Z. Wang, H. Chen, J. Hur, D. Triyoso, S. Consiglio, K. Tapily, R. Clark, G. Leusink, S. Yu, W. Chern, A. I. Khan, “The impacts of ferroelectric and interfacial layer thicknesses on ferroelectric FET design,” IEEE Electron Device Lett., vol. 42, no. 8, pp. 1156-1159, 2021.
  95. B. Lin, Y. Pang, B. Gao, J. Tang, D. Wu, T.-W. Chang, W.-E. Lin, X. Sun, S. Yu, M.-F. Chang, H. Qian, H. Wu, “A highly reliable RRAM physically unclonable function utilizing post-process randomness source,” IEEE Journal of Solid-State Circuits, vol. 56, no. 5, pp. 1641-1650, 2021.
  96. X. Han, A. Privat, K. E. Holbert, J.-S. Seo, S. Yu, H. J. Barnaby, “Total ionizing dose effect on multi-state HfOx-based RRAM synaptic array,” IEEE Trans. Nucl. Sci., vol. 68, no. 5, pp. 756-761, 2021.
  97. A. Kaul, M. S. Bakir, X. Peng, S. K. Rajan, S. Yu, “3D polylithic integration and thermal implications on BEOL RRAM performance,” Chip Scale Review Magazine, vol. 25, no. 4, pp. 17-24, 2021.
  98. Y.-C. Luo, J. Hur, P. Wang, A. I. Khan, S. Yu, “Non-volatile, small-signal capacitance in ferroelectric capacitors,” Appl. Phys. Lett., 117, 073501, 2020, Editor’s Pick.
  99. P. Wang, Z. Wang, X. Sun, J. Hur, S. Datta, A. I. Khan, S. Yu, “Investigating ferroelectric minor loop dynamics and history effect – Part I: device characterization,” IEEE Trans. Electron Devices, vol. 67, no. 9, pp. 3592-3597, 2020.
  100. P. Wang, Z. Wang, X. Sun, J. Hur, S. Datta, A. I. Khan, S. Yu, “Investigating ferroelectric minor loop dynamics and history effect – Part II: physical modeling and impact on neural network training,” IEEE Trans. Electron Devices, vol. 67, no. 9, pp. 3598-3604, 2020.
  101. P. Wang, Z. Wang, W. Shim, J. Hur, S. Datta, A. I. Khan, S. Yu, “Drain-erase scheme in ferroelectric field effect transistor – Part I: device characterization,” IEEE Trans. Electron Devices, vol. 67, no. 3, pp. 955-961, 2020.
  102. P. Wang, W. Shim, Z. Wang, J. Hur, S. Datta, A. I. Khan, S. Yu, “Drain-erase scheme in ferroelectric field effect transistor-Part II: 3D-NAND architecture for in-memory computing,” IEEE Trans. Electron Devices, vol. 67, no. 3, pp. 962-967, 2020.
  103. J. Hur, N. Tasneem, G. Choe, P. Wang, Z. Wang, A. I. Khan, S. Yu, “Direct comparison of ferroelectric properties in Hf0.5Zr0.5O2 between thermal and plasma-enhanced atomic layer deposition,” Nanotechnology, vol. 31, 505707, 2020.
  104. P. Wang, S. Yu, “Ferroelectric devices and circuits for neuro-inspired computing,” MRS Communications, vol. 10, no. 4, pp. 538–548, 2020, invited review.
  105. P. Wang, A. I. Khan, S. Yu, “Cryogenic behavior of NbO2 based threshold switching devices as oscillation neurons”, Appl. Phys. Lett., 116, 162108, 2020.
  106. W. Shim, Y. Luo, J.-S. Seo, S. Yu, “Investigation of read disturb and bipolar read scheme on multilevel RRAM based deep learning inference engine,” IEEE Trans. Electron Devices, vol. 67, no. 6, pp. 2318-2323, 2020.
  107. Y. Luo, Xu Han, Z. Ye, H. Barnaby, J.-S. Seo, S. Yu, “Array level programming of 3-bit per cell resistive memory and its application for deep neural network inference,” IEEE Trans. Electron Devices, vol. 67, no. 11, pp. 4621-4625, 2020.
  108. W. Shim, J.-S. Seo, S. Yu, “Two-step write-verify scheme and impact of the read noise in multilevel RRAM based inference engine,” Semicond. Sci. Technol., vol. 35, 115026, 2020.
  109. X. Peng, R. Liu, S. Yu, “Optimizing weight mapping and data flow for convolutional neural networks on processing-in-memory architectures,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 4, pp. 1333-1343, 2020.
  110. A. Lu, X. Peng, Y. Luo, S. Yu, “Benchmark of the compute-in-memory based DNN accelerator with area constraint,” IEEE Trans. VLSI Systems, vol. 28, no. 9, pp. 1945-1952, 2020.
  111. H. Jiang, X. Peng, S. Huang, S. Yu, “CIMAT: A compute-in-memory architecture for on-chip training based on transpose SRAM arrays,” IEEE Transactions on Computers, vol. 69, no. 7, pp. 944-954, 2020.
  112. Y. Luo, S. Yu, “Accelerating deep neural network in-situ training with non-volatile and volatile memory based hybrid precision synapses,” IEEE Transactions on Computers, vol. 69, no. 8, pp. 1113-1127, 2020.
  113. W. He, S. Yin, Y. Kim, X. Sun, J.-J. Kim, S. Yu, J.-S. Seo, “2-bit-per-cell RRAM based in-memory computing for area-/energy-efficient deep learning,” IEEE Solid-State Circuits Letters, vol. 3, pp. 194-197, 2020.
  114. S. Yin, X. Sun, S. Yu, J.-S. Seo, “High-throughput in-memory computing for binary deep neural networks with monolithically integrated RRAM and 90nm CMOS,” IEEE Trans. Electron Devices, vol. 67, no. 10, pp. 4185-4192, 2020.
  115. X. Si, J.-J. Chen, Y.-N. Tu, W.-H. Huang, J.-H. Wang, Y.-C. Chiu, W.-C. Wei, S.-Y. Wu, X. Sun, R. Liu, S. Yu, R.-S. Liu, C.-C. Hsieh, K.-T. Tang, Q. Li, M.-F. Chang “A twin-8T SRAM computation-in-memory unit-macro for multibit CNN based AI edge processors,” IEEE Journal of Solid-State Circuits, vol. 55, no. 1, pp. 189-202, 2020.
  116. X. Chen, S. Datta, X. S. Hu, M. Jerry, A. F. Laguna, K. Ni, M. Niemier, D. Reis, X. Sun, P. Wang, X. Yin, S. Yu, “The impact of ferroelectric FETs on digital and analog circuits and architectures,” IEEE Design & Test, vol. 37, no. 1, pp. 79-99, 2020, invited.
  117. Z. Wang, H. Ying, W. Chern, S. Yu, M. Mourigal, J. D. Cressler, A.I. Khan, “Cryogenic characterization of a ferroelectric field-effect-transistor,” Appl. Phys. Lett., 116, 042902, 2020.
  118. W. Zhang, B. Gao, J. Tang, P. Yao, S. Yu, M.-F. Chang, H.-J. Yoo, H. Qian, H. Wu, “Neuro-inspired computing chips,” Nature Electronics, vol. 3, no. 7, pp. 371-382, 2020, invited review.
  119. F. Cai, S. Kumar, T. V. Vaerenbergh, X. Sheng, R. Liu, C. Li, Z. Liu, M. Foltin, S. Yu, Q. Xia, J. J. Yang, R. Beausoleil, W. Lu, J. P. Strachan, “Power efficient combinatorial optimization using intrinsic noise in memristor Hopfield neural networks,” Nature Electronics, vol. 3, no. 7, pp. 409-418, 2020.
  120. J. Woo, P. Wang, S. Yu, “Integrated crossbar array with resistive synapses and oscillation neurons,” IEEE Electron Device Lett., vol. 40, no. 8, pp.1313-1316, 2019.
  121. X. Sun, S. Yu, “Impact of non-ideal characteristics of resistive synaptic devices on implementing convolutional neural networks,” IEEE J. Emerg. Sel. Topics Circuits Syst. (JETCAS),  vol. 9, no. 3, pp. 570-579, 2019.
  122. Y. Luo, P. Wang, X. Peng, X. Sun, S. Yu, “Benchmark of ferroelectric transistor based hybrid precision synapse for neural network accelerator,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JXCDC), vol. 5, no. 2, pp. 142 – 150, 2019.
  123. P.-Y. Chen, S. Yu, “Technological benchmark of analog synaptic devices for neuro-inspired architectures,” IEEE Design & Test, vol. 36, no. 3, pp. 31-38, 2019, invited.
  124. P. Wang, F. Xu, B. Wang, B. Gao, H. Wu, H. Qian, S. Yu, “3D NAND Flash for vector-matrix multiplication,” IEEE Trans. VLSI Systems, vol. 27, no. 4, pp. 988-991, 2019.
  125. J. Woo, S. Yu, “Impact of selector devices in analog RRAM based crossbar arrays for inference and training of neuromorphic system,” IEEE Trans. VLSI Systems, vol. 27, no. 9, pp. 2205-2212, 2019.
  126. Z. Ye, R. Liu, J. Taggart, H. Barnaby, S. Yu, “Evaluation of radiation effects in RRAM based neuromorphic computing system for inference,” IEEE Trans. Nucl. Sci., vol. 66, no. 1, pp. 97-103, 2019.
  127. S. Yin, Y. Luo, Y. Kim, W. He, X. Han, X. Sun, H. Barnaby, J.-J. Kim, S. Yu, J.-S. Seo, “Monolithically integrated RRAM and CMOS based in-memory computing optimizations for efficient deep learning,” IEEE Micro, vol. 39, no. 6, pp. 54-63, 2019, invited.
  128. M. Mao, X. Peng, R. Liu, J. Li, S. Yu, C. Chakrabarti, “MAX^2: An ReRAM-based neural network accelerator that maximizes data reuse and area utilization,” IEEE J. Emerg. Sel. Topics Circuits Syst. (JETCAS), vol. 9, no. 2, pp. 398-410, 2019.
  129. W.-S. Khwa, J.-J. Chen, J.-F. Li, X. Si, E.-Y. Yang, X. Sun, R. Liu, P.-Y. Chen, Q. Li, S. Yu, M.-F. Chang, “A dual-split 6T SRAM based computing-in-memory unit-macro with fully parallel product-sum operation for binarized DNN edge processors,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 11, pp. 4172-4185, 2019.
  130. R. Islam, H. Li, P.-Y. Chen, W. Wan, H.-Y. Chen, B. Gao, H. Wu, S. Yu, K. Saraswat, H.-S. P. Wong, “Device and materials requirements for neuromorphic computing,” Journal of Physics D: Applied Physics, vol. 52, 113001, 2019, invited review.
  131. F. Zhou, Z. Zhou, J. Chen, T. H. Choy, J. Wang, N. Zhang, Z. Lin, S. Yu, J. F. Kang, H.-S. P. Wong, Y. Chai, “Optoelectronic resistive random access memory for neuromorphic vision sensors,” Nature Nanotechnology, vol. 14, pp. 776-782, 2019.
  132. S. Yu, “Neuro-inspired computing with emerging non-volatile memory,” Proc. IEEE, vol. 106, no. 2, pp. 260-285, 2018. [Link].
  133. J. Woo, S. Yu, “Two-step read scheme in one-selector and one-RRAM crossbar based neural network for improved inference robustness,” IEEE Trans. Electron Devices, vol. 65, no. 12, pp. 5549-5553, 2018.
  134. P.-Y. Chen, X. Peng, S. Yu, “NeuroSim: A circuit-level macro model for benchmarking neuro-inspired architectures in online learning,” IEEE Trans. CAD,vol. 37, no. 12, pp. 3067-3080, 2018.
  135. J. Woo, S. Yu, “Comparative study of cross-point MRAM array with exponential and threshold selectors for read operation,” IEEE Electron Device Lett., vol. 39, no. 5, pp. 680-683, 2018.
  136. J. Woo, S. Yu, “Resistive memory based analog synapse: the pursuit for linear and symmetric weight update,” IEEE Nanotechnology Magazine, vol. 12, no. 3, pp. 36-44, 2018, invited review.
  137. R. Liu, P.-Y. Chen, X. Peng, S. Yu, “X-point PUF: exploiting sneak paths for a strong physical unclonable function design,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 10, pp. 3459-3468, 2018.
  138. S. Choi, S. H. Tan, Z. Li, Y. Kim, C. Choi, P.-Y. Chen, H. Yeon, S. Yu, J. Kim, “SiGe epitaxial memory for neuromorphic computing with reproducible high performance based on engineered dislocations,” Nature Materials, vol.17, pp. 335-340, 2018.
  139. M. Jerry, S. Dutta, A. Kazemi, K. Ni, J. Zhang, P.-Y. Chen, P. Sharma, S. Yu, X. S. Hu, M. Niemier, S. Datta, “A ferroelectric field effect transistor based synaptic weight cell,” Journal of Physics D: Applied Physics, vol. 51, 434001, 2018.
  140. M. Mao, S. Yu, C. Chakrabarti, “Design and analysis of energy-efficient and reliable 3D ReRAM cross-point array system,” IEEE Trans. VLSI Systems, vol. 26, no. 7, pp. 1290-1300, 2018.
  141. A. Tosson, S. Yu, M. H. Anis, L. Wei, “Proposing a solution for single-event upset in 1T1R RRAM memory arrays,” IEEE Trans. Nucl. Sci., vol. 65, no. 6, pp. 1239-1247, 2018.
  142. L. Xia, B. Li, T. Tang, P. Gu, P.-Y. Chen, S. Yu, Y. Cao, Y. Wang, Y. Xie, H. Yang, “MNSIM: simulation platform for memristor-based neuromorphic computing system,” IEEE Trans. CAD, vol. 37, no. 5, pp. 1009-1022, 2018.
  143. C. S. Thakur, J. Molin, G. Cauwenberghs, G. Indiveri, K. Kumar, N. Qiao, J. Schemmel, R. Wang, E. Chicca, J. O. Hasler, J.-S. Seo, S. Yu, Y. Cao, A. Van Schaik, R. Etienne Cummings, “Large-scale neuromorphic spiking array processors: a quest to mimic the brain”, Front. Neurosci., vol. 12, p. 891, 2018, invited review.
  144. L. Gao, P.-Y. Chen, S. Yu, “NbOx based oscillation neuron for neuromorphic computing,” Appl. Phys. Lett., 111, 103503, 2017.
  145. X. Sun, R. Liu, Y.-J. Chen, H.-Y. Chiu, W.-H. Chen, M.-F. Chang, S. Yu, “Low-VDD operation of SRAM synaptic array for implementing ternary neural network,” IEEE Trans. VLSI Systems, vol. 25, no. 10, pp. 2962-2965, 2017. 
  146. Z. Li, P.-Y. Chen, H. Xu, S. Yu, “Design of ternary neural network with 3D vertical RRAM array,” IEEE Trans. Electron Devices, vol. 64, no. 6, pp. 2721-2727, 2017.
  147. Z. Li, P.-Y. Chen, H. Liu, Q. Li, H. Xu, S. Yu, “Quasi-analytical model of 3D vertical RRAM array architecture for Mb-level design,” IEEE Trans. Electron Devices, vol. 64, no. 4, pp. 1568–1574, 2017.
  148. L. Gao, K. Holbert, S. Yu, “Total ionizing dose effects of gamma-ray radiation on NbOx based selector devices for crossbar array memory,” IEEE Trans. Nucl. Sci., vol. 64, no. 6, pp. 1535-1539, 2017.
  149. X. Peng, R. Madler, P.-Y. Chen, S. Yu, “Cross-point memory design challenges and survey of selector device characteristics,” Journal of Computational Electronics, vol. 16, no. 4, pp. 1167-1174, 2017, invited.
  150. N. Xu, P.-Y. Chen, J. Wang, W. Choi, K.-H. Lee, E. S. Jung, S. Yu, “Review of physics-based compact models for emerging nonvolatile memories,” Journal of Computational Electronics, vol. 16, no. 4, pp. 1257-1269, 2017, invited.
  151. W. Qian, P.-Y. Chen, R.  Karam, L. Gao, S. Bhunia, S. Yu, “Energy-efficient adaptive computing with multifunctional memory,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 2, pp. 191-195, 2017.
  152. M. Mao, P.-Y. Chen, S. Yu, C. Chakrabarti, “A multi-layer approach to designing energy-efficient and reliable ReRAM cross-point array system,” IEEE Trans. VLSI Systems, vol. 25, no. 5, pp. 1611-1621, 2017.
  153. Z. Xu, S. Skorheim, M. Tu, V. Berisha, S. Yu, J.-S. Seo, M. Bazhenov, Y. Cao, “Improving efficiency in sparse learning with the feedforward inhibitory motif,” Neurocomputing, vol. 267, pp. 141-151, 2017.
  154. A. Tosson, S. Yu, M. H. Anis, L. Wei, “A study of the effect of RRAM reliability soft errors on the performance of RRAM-based neuromorphic systems,” IEEE Trans. VLSI Systems, vol. 25, no. 11, pp. 3125-3137, 2017.
  155. Y. Pang, H. Wu, B. Gao, N. Deng, D Wu, R. Liu, S. Yu, A. Chen, H. Qian, “Optimization of RRAM-based physical unclonable function with a novel differential read-out method,” IEEE Electron Device Lett., vol. 38, no. 2, pp. 168-171, 2017.
  156. W. Wu, H. Wu, B. Gao, N. Deng, S. Yu, H. Qian, “Improving analog switching in HfOx based resistive memory with thermal enhanced layer,” IEEE Electron Device Lett., vol. 38, no. 8, pp. 1019-1022, 2017.
  157. S. Yu, P.-Y. Chen, “Emerging memory technologies: recent trends and prospects,” IEEE Solid State Circuits Magazine, vol. 8, no. 2, pp. 43-56, 2016, invited review. [Link]
  158. L. Gao, P.-Y. Chen, R. Liu, S. Yu, “Physical unclonable function exploiting sneak paths in resistive cross-point array,” IEEE Trans. Electron Devices, vol. 63, no. 8, pp. 3109-3115, 2016.
  159. L. Gao, P.-Y. Chen, S. Yu, “Demonstration of convolution kernel operation on resistive cross-point array,” IEEE Electron Device Lett., vol. 37, no. 7, 870-873, 2016.
  160. P.-Y. Chen, L. Gao, S. Yu, “Design of resistive synaptic array for implementing on-chip sparse learning,” IEEE Transactions on Multi-Scale Computing Systems, vol. 2, no. 4, pp. 257 – 264, 2016.
  161. P.-Y. Chen, Z. Li, S. Yu, “Design trade-offs of vertical RRAM based 3D cross-point array,”  IEEE Trans. VLSI Systems, vol. 24, no. 12, pp. 3460-3467, 2016. 
  162. R. Liu, H. Barnaby, S. Yu, “System-level analysis of single event upset susceptibility in RRAM architectures,” Semicond. Sci. Technol., vol. 31, no. 12, 124005, 2016.
  163. M. Mao, Y. Cao, S. Yu, C. Chakrabarti, “Optimizing latency, energy, and reliability of 1T1R ReRAM through cross-layer techniques,” IEEE J. Emerg. Sel. Topics Circuits Syst. (JETCAS), vol. 6, no. 3, 352-363, 2016.
  164. Z. Jiang, Y. Wu, S. Yu, L. Yang, K. Song, Z. Karim, and H.-S. P. Wong, “A compact model for metal oxide resistive random access memory (RRAM) with experiment verification,” IEEE Trans. Electron Devices, vol. 64, no. 5, pp. 1884-1892, 2016.
  165. Z. Chen, H. Li, H.-Y. Chen, B. Chen, R. Liu, P. Huang, F. Zhang, Z. Jiang, H. Ye, B. Gao, L. F. Liu, X. Y. Liu, J. F. Kang, H.-S. P. Wong, S.  Yu, “Disturbance characteristics of half-selected cells in cross-point resistive switching memory array,” Nanotechnology, vol. 27, 215204, 2016.
  166. L. Xia, P. Gu, B. Li, T. Tang, X. Yin, W. Huangfu, S. Yu, Y. Cao, Y. Wang, H. Yang, “Technological exploration of RRAM crossbar array for matrix-vector multiplication,” Journal of Computer Science and Technology, vol. 31, no. 1, pp. 3-19, 2016.
  167. R. Liu, H. Wu, Y. Pang, H. Qian, S. Yu, “Experimental characterization of physical unclonable function based on 1kb resistive random access memory arrays,” IEEE Electron Device Lett., vol. 36, no. 12, pp. 1380-1383, 2015.
  168. L. Gao, I-T. Wang, P.-Y. Chen, S. Vrudhula, J.-S. Seo, Y. Cao, T.-H. Hou, S. Yu, “Fully parallel write/read in resistive synaptic array for accelerating on-chip learning,” Nanotechnology, vol. 26, 455204, 2015.
  169. L. Gao, P.-Y. Chen, S. Yu, “Programming protocol optimization for analog weight tuning in resistive memories,” IEEE Electron Device Lett., vol. 36, no. 11, pp. 1157–1159, 2015.
  170. P.-Y. Chen, S. Yu, “Compact modeling of RRAM devices and its applications in 1T1R and 1S1R array design,” IEEE Trans. Electron Devices, vol. 62, no. 12, pp. 4022-4028, 2015.
  171. R. Liu, D. Mahalanabis, H. J. Barnaby, S. Yu, “Investigation of single-bit and multiple-bit upsets in oxide RRAM-based 1T1R and crossbar memory arrays,” IEEE Trans. Nucl. Sci., vol. 62, no. 5, pp. 2294-2301, 2015.
  172. R. Fang, W. Chen, L. Gao, W. Yu, S. Yu, “Low temperature characteristics of HfOx-based resistive random access memory,” IEEE Electron Device Lett., vol. 36, no. 6, pp. 567-569, 2015.
  173. D. Kadetotad, Z. Xu, A. Mohanty, P.-Y. Chen, B. Lin, J. Ye, S. Vrudhula, S. Yu, Y. Cao, J.-S. Seo, “Parallel architecture with resistive crosspoint array for dictionary learning acceleration,” IEEE J. Emerg. Sel. Topics Circuits Syst. (JETCAS),  vol. 5, no. 2, pp. 194-204, 2015.
  174. J.-S. Seo, B. Lin, M. Kim, P.-Y. Chen, D. Kadetotad, Z. Xu, A. Mohanty, S. Vrudhula, S. Yu, J. Ye, Y. Cao, “On-chip sparse learning acceleration with CMOS and resistive synaptic devices,”  IEEE Trans. Nanotechnol., vol. 14, no. 6, pp. 969-979, 2015.
  175. D. Mahalanabis, R. Liu, H. J. Barnaby, S. Yu, M. N. Kozicki, A. Mahmud, and E. Deionno, “Single event susceptibility analysis in CBRAM resistive memory arrays,” IEEE Trans. Nucl. Sci., vol. 62, no. 6, pp. 2606-2612, 2015.
  176. W. Chen, H. J. Barnaby, M. N. Kozicki, A. H. Edwards, Y. Gonzalez-Velo, R. Fang, K. E. Holbert, S. Yu, W. Yu, “A study of gamma-ray exposure of Cu-SiO2 programmable metallization cells”, IEEE Trans. Nucl. Sci., vol. 62, no. 6, pp. 2404 – 2411, 2015.
  177. C. Xu, D. Niu, Y. Zheng, S. Yu, and Y. Xie, “Impact of cell failure on reliable cross-point resistive memory design,” ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 20, no. 4, article 63, 2015.
  178. H. Li, B. Gao, H.-Y. Chen, Z. Chen, P. Huang, R. Liu, L. Zhao, Z. Jiang, L. F. Liu, X. Y. Liu, S. Yu, J. F. Kang, Y. Nishi, and H.-S. P. Wong, “Three-dimensional resistive memory arrays: from intrinsic switching behaviors to optimization guidelines ,” IEEE Trans. Electron Devices, vol. 62, no. 10, pp. 3160-3167, 2015.
  179. R. Fang, Y. Gonzalez-Velo, W. Chen, K. Holbert, M. Kozicki, H. Barnaby, S. Yu, “Total ionizing dose effect of γ-ray radiation on the switching characteristics and filament stability of HfOx resistive random access memory,” Appl. Phys. Lett., 104, 183507, 2014.
  180. Z. Xu, A. Mohanty, P.-Y. Chen, D. Kadetotad, B. Lin, J. Ye, S. Vrudhula, S. Yu, J.-S. Seo, Y. Cao, “Parallel programming of resistive cross-point array for synaptic plasticity,” Procedia Computer Science, vol. 41, pp. 126-133, 2014.
  181. L. Zhao, H.-Y. Chen, S.-C. Wu, Z. Jiang, S. Yu, T.-H. Hou, H.-S. P. Wong, and Y. Nishi, “Multi-level control of conductive nano-filament evolution in HfO2 ReRAM by pulse-train operations,” Nanoscale, vol, 11, pp. 5698-5702, 2014.
  182. B. Gao, B. Chen, R. Liu, F. Zhang, P. Huang, L. F. Liu, X. Y. Liu, J. F. Kang, H.-Y Chen, S. Yu, and H.-S. P. Wong, “3D cross-point array operation on AlOy/HfOx based vertical resistive switching memory,” IEEE Trans. Electron Devices, vol. 61, no. 5, pp. 1377 – 1381, 2014.
  183. B. Gao, Y. Bi, H.-Y. Chen, R. Liu, P. Huang, B. Chen, L. F. Liu, X. Y. Liu, S. Yu, H.-S. P. Wong, J. F. Kang, “Ultra-low energy three-dimensional oxide-based electronic synapses for implementation of robust high accuracy neuromorphic computation systems,” ACS Nano, vol. 8, no. 7, pp. 6998-7004, 2014.
  184. S. Yu, B. Gao, Z. Fang, H. Y. Yu, J. F. Kang, and H.-S. P. Wong, “Stochastic learning in oxide binary synaptic device for neuromorphic computing,” Front. Neurosci., vol. 7, 186, 2013.
  185. H.-Y. Chen, S. Yu, B. Gao, R. Liu, Z. Jiang, Y. Deng, B. Chen, J. F. Kang, and H.-S. P. Wong, “Experimental study of plane electrode thickness scaling for 3D vertical resistive random access memory,” Nanotechnology, vol. 24, 465201, 2013.
  186. D. Kuzum, S. Yu, and H.-S. P. Wong, “Synaptic electronics: materials, devices and applications,” Nanotechnology, vol. 24, 382001, 2013, invited review.
  187. S. Yu, B. Gao, Z. Fang, H. Y. Yu, J. F. Kang, and H.-S. P. Wong, “A low energy oxide-based electronic synaptic device for neuromorphic visual system with tolerance to device variation,” Adv. Mater., vol. 25, no. 12, pp. 1774-1779, 2013.
  188. S. Yu, H.-Y. Chen, B. Gao, J. F. Kang, and H.-S. P. Wong, “A HfOx based vertical resistive switching random access memory for bit-cost-effective three-dimensional cross-point architecture,” ACS Nano, vol. 7, no. 3, pp. 2320-2325, 2013.
  189. H. Tian, H.-Y. Chen, B. Gao, S. Yu, J. Liang, Y. Yang, D. Xie, J. Kang, T.-L. Ren, Y. Zhang, and H.-S. P. Wong, “Monitoring oxygen movement by Raman spectroscopy of resistive random access memory with a graphene-inserted electrode,” Nano Lett., vol. 13, no. 2, pp. 651-657, 2013.
  190. X. Guan, S. Yu, and H.-S. P. Wong, “A SPICE compact model of metal oxide resistive switching memory with variations,” IEEE Electron Device Lett., vol. 33, no. 10, pp. 1405-1407, 2012.
  191. X. Guan, S. Yu, and H.-S. P. Wong, “On the switching parameter variation of metal oxide RRAM – part I: physical modeling and simulation methodology,” IEEE Trans. Electron Devices, vol. 59, no. 4, pp. 1172-1182, 2012.
  192. S. Yu, X. Guan, and H.-S. P. Wong, “On the switching parameter variation of metal oxide RRAM – part II: model corroboration and device design strategy,” IEEE Trans. Electron Devices, vol. 59 no. 4, pp. 1183-1189, 2012.
  193. S. Yu, R. Jeyasingh, Y. Wu, and H.-S. P. Wong, “Characterization of low-frequency noise in the resistive switching of transition metal oxide HfO2,” Phys. Rev. B, vol. 85, 045324, 2012.
  194. S. Yu, Y. Y. Chen, X. Guan, H.-S. P. Wong, J. A. Kittl, “A Monte Carlo study of the low resistance state retention of HfOx based resistive switching memory,” Appl. Phys. Lett., vol. 100, 043507, 2012.
  195. D. Kuzum, R. Jeyasingh, S. Yu, and H.-S. P. Wong, “Low energy, robust neuromorphic computation using synaptic devices,” IEEE Trans. Electron Devices, vol. 59, no. 12, pp. 3489-3494, 2012.
  196. H.-S. P. Wong, H.-Y. Lee, S. Yu, Y.-S. Chen, Y. Wu, P.-S. Chen, B. Lee, F. T. Chen, and M.-J. Tsai, “Metal Oxide RRAM,” Proc. IEEE, vol. 100, no. 6, pp. 1951-1970, 2012, invited review.
  197. S. Yu, R. Jeyasingh, Y. Wu, and H.-S. P. Wong, “AC conductance measurement and analysis of the conduction processes in HfOx based resistive switching memory,” Appl. Phys. Lett., vol. 99, 232105, 2011.
  198. S. Yu, X. Guan, and H.-S. P. Wong, “Conduction mechanism of TiN/HfOx/Pt resistive switching memory: a trap-assisted-tunneling model,” Appl. Phys. Lett., vol. 99, 063507, 2011.
  199. S. Yu, Y. Wu, and H.-S. P. Wong, “Investigating the switching dynamics and multilevel capability of bipolar metal oxide resistive switching memory,” Appl. Phys. Lett., vol. 98, 103514, 2011.
  200. S. Yu, Y. Wu, R. Jeyasingh, D. Kuzum, and H.-S. P. Wong, “An electronic synapse device based on metal oxide resistive switching memory for neuromorphic computation”, IEEE Trans. Electron Devices, vol. 58, no. 8, pp. 2729-2737, 2011.
  201. S. Yu, and H.-S. P. Wong, “Compact modeling of conducting bridge random access memory (CBRAM),” IEEE Trans. Electron Devices, vol. 58, no. 5, pp. 1352-1360, 2011.
  202. Y. Wu, S. Yu, B. Lee, and H.-S. P. Wong, “Low-power TiN/Al2O3/Pt resistive switching device with sub-20 uA switching current and gradual resistance modulation,” J. Appl. Phys., vol. 110, 094104, 2011.
  203. Y. Chai, Y. Wu, K. Takei, H.-Y. Chen, S. Yu, P. C. H. Chan, A. Javey, and H.-S. P. Wong, “Nanoscale bipolar and complementary resistive switching memory based on amorphous carbon,” IEEE Trans. Electron Devices, vol. 58, no. 11, pp. 3933-3939, 2011.
  204. Y. Yang, S. Yu, L. Zeng, G. Du, J. F. Kang, Y. Zhao, R. Q. Han, and X. Y. Liu, “Variability induced by line edge roughness in double-gate dopant-segregated Schottky MOSFETs,” IEEE Trans. Nanotechnol., vol. 10, no. 2, pp. 244-249, 2011.
  205. S. Yu, and H.-S. P. Wong, “A phenomenological model for the reset mechanism of metal oxide RRAM,” IEEE Electron Device Lett., vol. 31, no. 12, pp.1455-1457, 2010.
  206. S. Yu, J. Liang, Y. Wu, and H.-S. P. Wong, “Read/write schemes analysis for the novel complementary resistive switches in passive crossbar memory arrays,” Nanotechnology, vol. 21, 465202, 2010.
  207. S. Yu, B. Gao, H. B. Dai, B. Sun, L. F. Liu, X. Y. Liu, R. Q. Han, J. F. Kang, and B. Yu, “Improved uniformity of resistive switching behaviors in HfO2 thin films with embedded Al layers,” Electrochem. Solid-State Lett., vol. 13, H36-H38, 2010.
  208. S. Yu, Y. Zhao, L. Zeng, G. Du, J. F. Kang, R. Q. Han, and X. Y. Liu, “Impact of line edge roughness on double-gate Schottky barrier field-effect transistors,” IEEE Trans. Electron Devices, vol. 56, no. 6, pp. 1211-1219, 2009.
  209. S. Yu, Y. Zhao, G. Du, J. F. Kang, R. Q. Han, and X. Y. Liu, “The impact of line edge roughness on the stability of a FinFET SRAM,” Semicond. Sci. Technol., vol. 24, 025005, 2009.
  210. S. Yu, Y. Zhao, G. Du, J. F. Kang, R. Q. Han, and X. Y. Liu, “Triple-gate FinFETs with fin-thickness optimization to reduce the impact of fin line edge roughness,” Jpn. J. Appl. Phys., vol.48, 04C052, 2009.

Conference papers:

  1. W.-H. Huang, J. Jia, Y. Kong, F. Waqar, T.-H. Wen, M.-F. Chang, S. Yu, “Hardware acceleration of Kolmogorov-Arnold Network (KAN) for lightweight edge inference,” ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) 2025, Tokyo, Japan.
  2. J. Lee, C. Zhang, M. Shon, J. Read, S. Deng, O. Phadke, P. V. Ravindran, M. Tian, Y.-C. Luo, T.-H. Kim, A. I. Khan, S. Datta, S. Yu, “BEOL-compatible non-volatile capacitive synapse with ALD W-doped In2O3 semiconductor layer,” IEEE International Electron Devices Meeting (IEDM) 2024, San Francisco, USA.
  3. J. Kwak, J. Shin, S. Deng, G. Jeong, J. Sharda, S. Datta, S. Yu, “Bias temperature instability analysis of oxide power transistors for BEOL on-chip voltage converter in thermally-constrained H3D systems,” IEEE International Electron Devices Meeting (IEDM) 2024, San Francisco, USA.
  4. S. Deng, J. Shin, C. Zhang, H. Park, O. Phadke, J. Kwak, S. Yu, S. Datta, “Boosted performance and enhanced reliability of BEOL-compatible dual-gate oxide power transistors for on-chip DC-DC voltage conversion,” IEEE International Electron Devices Meeting (IEDM) 2024, San Francisco, USA.
  5. E. Sarkar, C. Zhang, D. Chakraborty, F. Waqar, S. Kirtania, K. A. Aabrar, H. Park, J. Shin, M. Tian, A. I. Khan, S. Yu, S. Datta, “First demonstration of W-doped In2O3 gate-all-around (GAA) nanosheet FET with improved performance and record threshold voltage stability,” IEEE International Electron Devices Meeting (IEDM) 2024, San Francisco, USA.
  6. S. G. Kirtania, O. Phadke, E. Sarker, K. A. Aabrar, D. Chakraborty, F. Waqar, S. Jaewon, T. Pantha, S. Dutta, A. I. Khan, S. Yu, S. Datta, “Amorphous indium oxide channel FeFETs with write voltage of 0.9V and endurance >1012 for refresh-free 1T-1FeFET embedded memory,” IEEE International Electron Devices Meeting (IEDM) 2024, San Francisco, USA.
  7. N. Afroze, A. Padovani, J. Choi, P. G. Ravikumar, Y.-H. Kuo, C. Zhang, T. Song, M. Tian, E. Sarkar, M. Noor, P. V. Ravindran, K. A. Aabrar, B. Yildiz, S. Mahapatra, A. Kummel, K. Cho, S. Yu, S. Datta, J. H. Lee, L. Larcher, G. Thareja, A. I. Khan, “Self-healing ferroelectric capacitors with ~1000x endurance improvement at high temperatures (85–125˚C),” IEEE International Electron Devices Meeting (IEDM) 2024,San Francisco, USA.
  8. J. Duan, Y. Xu, Z. Zhao, A. Lu, J. Read, M. Imani, T. Kampfe, M. Niemier, X. Gong, S. Yu, V. Narayanan, K. Ni, “Variation tolerant and energy-efficient charge domain compute-in-memory array with binary and multi-level cell ferroelectric FET,” IEEE International Electron Devices Meeting (IEDM) 2024, San Francisco, USA.
  9. S. Mukherjee, J. Bizindavyi, S. Clima, Y. Xiang, M. Popovici, A. Belmonte, R. Izmailov, J. Stiers, A. Kruv, S. Subhechha, H. Dekkers, G. S. Kar, G. De, N. Ronchi, Z. Belkhiri, G. Van den Bosch, M. Rosmeulen, F. Catthoor, imec, S. Yu, V. Afanas’ev, J. Van Houdt, “Improved capacitive memory window for non-destructive read in HZO-based ferroelectric capacitors with incorporation of semiconducting IGZO,” IEEE International Electron Devices Meeting (IEDM) 2024, San Francisco, USA.
  10. S. Deng, J. Kwak, J. Lee, D. Chakraborty, J. Shin, O. Phadke, S. G. Kirtania, C. Zhang, K. A. Aabrar, S. Yu, S. Datta, “Demonstration of on-chip switched-capacitor DC-DC converters using BEOL compatible oxide power transistors and superlattice MIM capacitors,” IEEE Symposium on VLSI Technology and Circuits (VLSI) 2024, Hawaii, USA.
  11. P. Vanna-Iampikul, H. Yang, J. Kwak, J. X. Hu, A. Rahman, N. E. Bethur, C. Hao, S. Yu, S.-K. Lim, “A design methodology for back-side power and clock routing co-optimization,” IEEE Symposium on VLSI Technology and Circuits (VLSI) 2024, Hawaii, USA, invited.
  12. M. Manley, A. Kaul, J. Read, Y. Luo, X. Peng, S. Yu, M. S. Bakir, “Co-optimization for robust power delivery design in 3D-heterogeneous integration of compute-in-memory accelerators,” IEEE Symposium on VLSI Technology and Circuits (VLSI) 2024, Hawaii, USA, invited.
  13. S. Datta, S. Yu, A. I. Khan, S. Deng, K. A. Aabrar, J. Kwak, “Amorphous oxide semiconductors for monolithic 3D integrated circuits,” IEEE Symposium on VLSI Technology and Circuits (VLSI) 2024, Hawaii, USA, invited.
  14. C.-C. Wang, C.-C. Kuo, C.-H. Wu, A. Lu, H.-Y. Lee, C.-F. Hsu, P.-J. Tzeng, T.-Y. Lee, F.-R. Hou, M.-H. Chang, S.-C. Lai, K.-I. Goto, S. Yu, C.-I. Wu, C.-T. Lin, Y.-M. Lin, X.-Y. Bao, “P-type SnO semiconductor transistor and application,” IEEE Symposium on VLSI Technology and Circuits (VLSI) 2024, Hawaii, USA, invited.
  15. A. Lu, J. Lee, Y.-C. Luo, H. Li, I. Young, S. Yu, “Digital CIM with noisy SRAM bit: A compact clustered annealer for large-scale combinatorial optimization,” ACM/IEEE Design Automation Conference (DAC) 2024, San Francisco, CA.
  16. J. Son, J. Y. Park, T. Lee, S. Woo, S. Yu, “Modeling row hammer effect in 3D capacitor-less DRAM using triple-gated silicon nanosheet device,” IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 2024, San Jose. CA.
  17. T.-H. Kim, Y.-C. Luo, O. Phadke, J. Read, S. Yu, “Engineering nvCap from FEOL to BEOL with ferroelectric small-signal non-destructive read,” IEEE International Memory Workshop (IMW) 2024, Seoul, South Korea, invited.
  18. D. Das, L. Fernandes, P. V. Ravindran, T. Song, C. Park, N. Afroze, M. Tian, H. Chen, W. Chern, K. Kim, J. Woo, S. Lim, K. Kim, W. Kim, D. Ha, S. Yu, S. Datta, A. I. Khan, “Design framework for ferroelectric gate stack engineering of vertical NAND structures for efficient TLC and QLC operation,” IEEE International Memory Workshop (IMW) 2024, Seoul, South Korea.
  19. J. Lee, S. Deng, J. Kwak, M. Shon, S. Datta, S. Yu, “Optimization of backside of silicon-compatible high voltage superlattice capacitor for 12V-to-6V on-chip voltage conversion,” IEEE Device Research Conference (DRC) 2024, College Park, MD.
  20. S. Deng, J. Kwak, J. Lee, S. Yu, S. Datta, “BEOL-compatible on-chip DC-DC converters,” IEEE International Interconnect Technology Conference (IITC) 2024, San Jose, CA.
  21. J. Sharda, P.-K. Hsu, S. Yu, “Accelerator design using 3D stacked capacitorless DRAM for large language models,” IEEE International Conference on Artificial Intelligence Circuits & Systems (AICAS) 2024, Abu Dhabi, UAE.
  22. J. Kwak, G. Choe, J. Lee, S. Yu, “Monolithic 3D transposable 3T embedded DRAM with back-end-of-line oxide channel transistor,” IEEE International Symposium on Circuits and Systems (ISCAS) 2024, Singapore.
  23. J. Jia, Z. Jia, O. Phadke, G. Choe, Y. Shi, S. Yu, “A reconfigurable bandpass filter with ferroelectric devices for intracardiac electrograms monitoring,” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) 2024, Springfield, MA.
  24. J. Sharda, Q. Wu, S. Chang, S. Yu, “Impact of in-pixel processing circuit non-idealities on multi-object tracking accuracy for autonomous driving,” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) 2024, Springfield, MA.
  25. M. Shon, J. Lee, S. Yu, “3D digital compute-in-memory benchmark with A5 CFET technology,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) 2024, Taipei, Taiwan.
  26. Y.-C. Luo, J. Read, A. Lu, S. Yu, “A cross-layer framework for design space and variation analysis of non-volatile ferroelectric capacitor-based compute-in-memory accelerators,” ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) 2024, Incheon, South Korea.
  27. J. Read, Y.-C. Luo, A. Lu, S. Yu, “A cross-layer framework for design space and variation analysis of non-volatile ferroelectric capacitor-based compute-in-memory accelerators,” Government Microcircuit Applications and Critical Technology Conference (GOMACTech) 2024, Charleston, SC.
  28. O. Phadke, H. Mulaosmanovic, S. Dunkel, S. Beyer, S. Yu, “Reliability assessment of ferroelectric nvCAP for small-signal capacitive read-out,” IEEE International Reliability Physics Symposium (IRPS) 2024, Dallas, TX.
  29. X. Wu, L. Upton, P.-K. Hsu, J. Chen, S. Yu, H.-S. P. Wong, “A comparative study of HBL and VBL 3D DRAM: signal margin, bit-cell density, and scalability,” IEEE Silicon Nanoelectronics Workshop (SNW) 2024, Hawaii, USA.
  30. C. Park, P. V. Ravindran, D. Das, P. G. Ravikumar, W. Chern, S. Yu, A. I. Khan, “Plasma-enhanced atomic layer deposition based FeFETs,” IEEE Silicon Nanoelectronics Workshop (SNW) 2024, Hawaii, USA.
  31. P. G. Ravikumar, P. V. Ravindran, K. A. Aabrar, T. Song, S. G. Kirtania, D. Das, C. Park, N. Afroze, M. Tian, S. Yu, A. E. Islam, S. Datta, S. Mahapatra, A. I. Khan, “Comprehensive time-dependent dielectric breakdown (TDDB) characterization of ferroelectric capacitors under bipolar stress conditions,” IEEE International Reliability Physics Symposium (IRPS) 2024, Dallas, TX.
  32. S. E. Wodzro, O. Phadke, S. Datta, S. Yu, “Modeling single-event-effects in silicon bulk FeFET,” IEEE Semiconductor Interface Specialists Conference (SISC) 2024, San Diego, CA.
  33. O. Phadke, T.-H. Kim, Y.-C. Luo, S. Yu, “Ferroelectric nonvolatile capacitive synapse for charge domain compute-in-memory,” Electrochemical Society (ECS) Spring Meeting 2024, San Francisco, CA, invited.
  34. S. Deng, J. Kwak, J. Lee, K. A. Aabrar, T.-H. Kim, S. Kirtania, G. Choe, C. Zhang, W. Li, O. Phadke, S. Yu, S. Datta, “BEOL compatible oxide power transistors for on-chip voltage conversion in heterogenous 3D (H3D) integrated circuits,” IEEE International Electron Devices Meeting (IEDM) 2023, San Francisco, USA.
  35. P. G. Ravikumar, C. Park, P. V. Ravindran, N. Afroze, M. Tian, W. Chern, S. Datta, S. Yu, S. Mahapatra, A. I. Khan, “First write pulse-induced interface damage in ferroelectric field-effect transistors,” IEEE International Integrated Reliability Workshop(IIRW) 2024, Lake Tahoe, CA.
  36. D. Das, H. Park, Z. Wang, C. Zhang, P. V. Ravindran, C. Park, N. Afroze, P.-K. Hsu, M. Tian, H. Chen, W. Chern, S. Lim, K. Kim, K. Kim, W. Kim, D. Ha, S. Yu, S. Datta, A. I. Khan, “Ferroelectric Gate Stack Engineering with Tunnel Dielectric Insert for Achieving High Memory Window in FEFETs for NAND Applications,” IEEE Electron Devices Technology and Manufacturing Conference (EDTM) 2024, Bangalore, India.
  37. S. Mukherjee, J. Bizindavyi, S. Clima, M. I. Popovici, Y. Xiang, F. Catthoor, S. Yu, V. V. Afanas’ev, J. Van Houdt, “Non-destructive read and capacitive memory window in ferroelectric capacitors intended for energy-efficient CIM and memory applications,” International Conference on Neuromorphic Computing and Engineering (ICNCE) 2024, Aachen, Germany.
  38. S. Ray, S. Mukherjee, F. G. Redondo, S. Yu, F. Catthoor, J. Van Houdt, D. Biswas, “Evaluation of a ferroelectric capacitor-based compute-in-memory framework,” IEEE International Conference on Electronics Circuits and Systems (ICECS) 2024, Nancy, France.
  39. K. A. Aabrar, S. Kirtania, S. Deng, G. Choe, A. I. Khan, S. Yu, S. Datta, “Improved reliability and enhanced performance in BEOL compatible W-doped In2O3 dual-gate transistor,” IEEE International Electron Devices Meeting (IEDM) 2023, San Francisco, USA.
  40. D. Das, H. Park, Z. Wang, C. Zhang, P. Ravindran, C. Park, N. Afroze, P.-K. Hsu, M. Tian, H. Chen, W. Chern, S. Lim, K. Kim, K. Kim, W. Kim, D. Ha, S. Yu, S. Datta, A. I. Khan, “Experimental demonstration and modeling of a ferroelectric gate stack with a tunnel dielectric insert for NAND applications,” IEEE International Electron Devices Meeting (IEDM) 2023, San Francisco, USA.
  41. Z. Zhao, Y. Xu, J. Read, P.-K. Hsu, Y. Qin, T. Huang, S. Lim, K. Kim, K. Kim, W. Kim, D. Ha, T. Kämpfe, S. George, X. Gong, S. Datta, S. Yu, V. Narayanan, K. Ni, “In-situ encrypted NAND FeFET array for secure storage and compute-in-memory,” IEEE International Electron Devices Meeting (IEDM) 2023, San Francisco, USA.
  42. S. Mukherjee, J. Bizindavyi, Y. Luo, S. Clima, J. Read, M. Popovici, Y. Xiang, N. Bazzazian, A. Belmonte, R. Delhougne, G. Sankar Kar, F. Catthoor, V. Afanas’ev, S. Yu, J. Van Houdt, “Pulse-based capacitive memory window with high non-destructive read endurance in fully BEOL compatible ferroelectric capacitors,” IEEE International Electron Devices Meeting (IEDM) 2023, San Francisco, USA.
  43. W. Li, Y. Luo, S. Yu, “RAWAtten: Reconfigurable accelerator for window attention in hierarchical vision transformers,” ACM/IEEE Design, Automation & Test in Europe (DATE) 2023, Antwerp, Belgium.
  44. W. He, J. Meng, S. K. Gonugondla, S. Yu, N. R. Shanbhag, J.-S. Seo, “PRIVE: Efficient RRAM programming with chip verification for RRAM-based in-memory computing acceleration,” ACM/IEEE Design, Automation & Test in Europe (DATE) 2023, Antwerp, Belgium.
  45. W. Li, J. Lee, S. Yu, “Optimization strategies for digital compute-in-memory from comparative analysis with systolic array,” IEEE International Conference on Artificial Intelligence Circuits & Systems (AICAS) 2023, Hangzhou, China.
  46. W. Li, X. Zhang, J. Lee, F. L. Degertekin, S. Li, S. Yu, “Enabling ultra-low power ultrasound imaging with compute-in-memory sparse reconstruction accelerator,” IEEE Biomedical Circuits and Systems Conference (Bio-CAS) 2023, Toronto, Canada.
  47. O. Phadke, K. A. Aabrar, Y.-C. Luo, S. G. Kirtania, A. I. Khan, S. Datta, S. Yu, “Low-frequency noise characteristics of ferroelectric field-effect transistors,” IEEE International Reliability Physics Symposium (IRPS) 2023, Monterey, CA.
  48. J. Sharda, M. Manley, A. Kaul, W. Li, M. Bakir, S. Yu, “Thermal modeling of 2.5D integrated package of CMOS image sensor and FPGA for autonomous driving,” IEEE Electron Devices Technology and Manufacturing Conference (EDTM) 2023, Seoul, Korea.
  49. S. Woo, G. Choe, A. I. Khan, S. Datta, S. Yu, “Design of ferroelectric-metal field-effect transistor for multi-level-cell 3D NAND Flash,” IEEE International Memory Workshop (IMW) 2023, Monterey, CA.
  50. J. Read, W. Li, S. Yu, “Enabling long-term robustness in RRAM-based compute-in-memory edge devices,” IEEE International Symposium on Circuits and Systems (ISCAS) 2023, Monterey, CA.
  51. J. Kwak, W. Li, S. Yu, “A reconfigurable monolithic 3D switched-capacitor DC-DC converter with back-end-of-line oxide channel transistor,” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) 2023, Phoenix, AZ, best paper award.
  52. P.-K. Hsu, W. Xu, T. Rosing, S. Yu, “An in-storage processing architecture with 3D NAND heterogeneous integration for spectra open modification search,” ACM/IEEE International Symposium on Memory Systems (MEMSYS) 2023, Washington DC.
  53. E. G. Weinstock, Y. Tan, W. Li, S Yu, “Machine learning algorithm co-design for a 40 nm RRAM analog compute-in-memory accelerator,” IEEE International Opportunity Research Scholars Symposium (ORSS) 2023, Atlanta, GA.
  54. Y.-C. Luo, O. Phadke, T.-H. Kim, S. Yu, “Programmable non-volatile gate-to-source/drain capacitance of FeFET for capacitive synapse,” IEEE Non-Volatile Memory Technology Symposium (NVMTS) 2023, Leuven, Belgium.
  55. T.-H. Kim, O. Phadke, Y.-C. Luo, S. Yu, “Tunable non-volatile gate-to-source/drain capacitance of FeFET for capacitive synapse,” IBM AI Hardware Forum 2023, Yorktown Heights, NY.
  56. S. Mukherjee, J. Bizindavyi, S. Clima, M. I. Popovici, X. Piao, K. Katcko, F. Catthoor, S. Yu, V. Afanas’ev, J. Van Houdt, “On the non-volatile ferroelectric capacitive memory window and how to achieve it,” IEEE Non-Volatile Memory Technology Symposium (NVMTS) 2023, Leuven, Belgium.
  57. S. Mukherjee, J. Bizindavyi, S. Clima, Y. Xiang, M. I. Popovici, P. Bagul, G. De, N. Bazzazian, F. Catthoor, S. Yu, V. V. Afanas’ev, J. Van Houdt, “Ferroelectric capacitive memory window: asymmetry engineering, pulse-based nondestructive read, and analytical understanding from thermodynamic potential framework,” IEEE Semiconductor Interface Specialists Conference (SISC) 2023, San Diego, CA.
  58. S. G. Kirtania, K. A. Aabrar, A. I. Khan, S. Yu, S. Datta, “Cold FeFET as an embedded non-volatile memory with unlimited cycling endurance,” IEEE Symposium on VLSI Technology and Circuits (VLSI) 2023, Kyoto, Japan.
  59. M. Lee, A. Lu, M. Mukherjee, S. Yu, S. Mukhopadhyay, “CLUE: Cross-Layer Uncertainty Estimator for Reliable Neural Perception Using Processing-In-Memory Accelerators,” International Joint Conference on Neural Networks (IJCNN) 2023, Queensland, Australia.
  60. N. Tasneem, Z. Wang, S. F. Lombardo, H. Chen, S. Yu, W. Chern, A. I. Khan, “Charge trapping effects on memory window in ferroelectric field effect transistors,” IEEE International Symposium on Applications of Ferroelectrics (ISAF) 2023, Cleveland, OH.
  61. A. Lu, J. Hur, Y.-C. Luo, H. Li, D. E. Nikonov, I. Young, Y.-K. Choi, S. Yu, “Scalable in-memory clustered annealer with temporal noise of FinFET for the travelling salesman problem,” IEEE International Electron Devices Meeting (IEDM) 2022, San Francisco, USA.
  62. K. A. Aabrar, J. Read, S. G. Kirtania, S. Stepanoff, D. E. Wolfe, S. Yu, S. Datta, “Total ionizing dose effect in tri-gate silicon ferroelectric transistor memory,” IEEE International Electron Devices Meeting (IEDM) 2022, San Francisco, USA.
  63. M. Passlack, N. Tasneem, Z. Wang, K. A. Aabrar, J. Hur, H. Chen, V. D.-H. Hou, C.-S. Chang, M.-F. Chang, S. Yu, W. Chern, S. Datta, A. I. Khan, “Direct quantitative extraction of internal variables from measured PUND characteristics providing new key insights into physics and performance of silicon and oxide channel ferroelectric FETs,” IEEE International Electron Devices Meeting (IEDM) 2022, San Francisco, USA.
  64. G. Choe, P. V. Ravindran, A. Lu, J. Hur, M. Lederer, A. Reck, S. Lombardo, N. Afroze, J. Kacher, A. I. Khan, S. Yu, “Machine learning assisted statistical variation analysis of ferroelectric transistors: from experimental metrology to predictive modeling,” IEEE Symposium on VLSI Technology and Circuits (VLSI) 2022, Hawaii, USA.
  65. H. Jiang, W. Li, S. Huang, S. Yu, “A 40nm analog-input ADC-free compute-in-memory RRAM macro with pulse-width modulation between sub-arrays,” IEEE Symposium on VLSI Technology and Circuits (VLSI) 2022, Hawaii, USA, highlight paper.
  66. K. A. Aabrar, S. G. Kirtania, A. Lu, A. Khanna, W. Chakraborty, M. San Jose, S. Yu, S. Datta, “A thousand state superlattice(SL) FeFET analog weight cell,” IEEE Symposium on VLSI Technology and Circuits (VLSI) 2022, Hawaii, USA.
  67. A. Khanna, H. Ye, y. Luo, G. Bajpai, M. San Jose, W. Chakraborty, S. Yu, P. Fay, S. Datta, “BEOL compatible ferroelectric routers for run-time reconfigurable compute-in-memory accelerators,” IEEE Symposium on VLSI Technology and Circuits (VLSI) 2022, Hawaii, USA.
  68. X. Lyu, P. R. Shrestha, M. Si, P. Wang, J. Li, K. P. Cheung, S. Yu, P. D. Ye, “Determination of domain wall velocity and nucleation time by switching dynamics studies of ferroelectric Hafnium Zirconium oxide,” IEEE Symposium on VLSI Technology and Circuits (VLSI) 2022, Hawaii, USA.
  69. W. Li, J. Read, H. Jiang, S. Yu, “A 40nm RRAM compute-in-memory macro with parallelism-preserving ECC for iso-accuracy voltage scaling,” IEEE European Solid-State Circuits Conference (ESSCIRC) 2022, Milan, Italy.
  70. Y. Luo, P. Kumar, Y.-C. Liao, W. Tsai, S. X. Wang, A. Naeemi, S. Yu, “Performance benchmarking of spin-orbit transfer magnetic RAM (SOT-MRAM) for deep neural network (DNN) accelerators,” IEEE International Memory Workshop (IMW) 2022, Dresden, Germany, best student paper award.
  71. P.-K. Hsu, S. Yu, “In-memory 3D NAND Flash hyperdimensional computing engine for energy-efficient SARS-CoV-2 genome sequencing,” IEEE International Memory Workshop (IMW) 2022, Dresden, Germany.
  72. W. Li, Q. Wu, J. Sharda, S. Chang, S. Yu, “Temporal frame filtering with near-pixel compute for autonomous driving,” IEEE International Conference on Artificial Intelligence Circuits & Systems (AICAS) 2022, Incheon, Korea.
  73. Y.-C. Luo, H. Ye, W. Chakraborty, J. Hur, P. V. Ravindran, A. I. Khan, S. Datta, S. Yu, “Low-frequency noise characteristics of BEOL-compatible IWO transistor,” IEEE Silicon Nanoelectronics Workshop (SNW) 2022, Hawaii, USA.
  74. J. Kwak, G. Choe, S. Yu, “A monolithic 3D design technology co-optimization with back-end-of-line oxide channel transistor”, ACM/IEEE International Symposium on Nanoscale Architectures (NANOARCH) 2022, virtual.
  75. D. S. Kang, S. Yu, “Design-technology co-optimization for cryogenic tensor processing unit,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) 2022, virtual.
  76. J. Read, W. Li, S. Yu, “A method for reverse engineering neural network parameters from compute-in-memory accelerators,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2022, virtual.
  77. Y.-C. Luo, S. Yu, “Challenges and opportunities of monolithic 3D computing-in-memory technology”, International Conference on Solid State Devices and Materials (SSDM) 2022, virtual, invited.
  78. J. Sharda, W. Li, S. Yu, “Temporal frame filtering for autonomous driving using 3D-stacked global shutter CIS with IWO buffer memory and near-pixel compute,” IBM AI Hardware Forum 2022, Yorktown Heights, NY.
  79. C. Park, D. Das, J. Hur, N. Tasneem, S. F. Lombardo, W. Chern, S. Yu, A. I. Khan, “Oxygen-scavenging effect on Si and Ge substrates with Hf0.5Zr0.5O2 ferroelectric films for ultra-low write voltage”, IEEE Semiconductor Interface Specialists Conference (SISC) 2022, San Diego, CA.
  80. J. Meng, I. Yeo, W. Shim, S. Yu, J.-S. Seo, “Sparse and robust RRAM-based efficient in-memory computing for deep neural network inference,” IEEE International Reliability Physics Symposium (IRPS) 2022, Dallas, TX, invited.
  81. Z. Wang, N. Tasneem, J. Hur, H. Chen, S. Yu, W. Chern, A. I. Khan, “Standby bias improves the endurance in ferroelectric field effect transistors due to fast neutralization of interface traps,” IEEE International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2022, virtual, invited.
  82. Z. Wang, N. Tasneem, H. Chen, S. Yu, W. Chern, A. I. Khan, “Improved endurance with electron-only switching in ferroelectric devices”, IEEE Device Research Conference (DRC) 2022, Columbus, OH.
  83. Y. Luo, S. Dutta, A. Kaul, S.-K. Lim, M. S. Bakir, S. Datta, S. Yu, “Monolithic 3D compute-in-memory accelerator with BEOL transistor based reconfigurable interconnect,” IEEE International Electron Devices Meeting (IEDM) 2021, San Francisco, USA, invited.
  84. Y.-C. Luo, J. Hur, T.-H. Wang, A. Lu, S. Li, A. I. Khan, S. Yu, “Experimental demonstration of non-volatile capacitive crossbar array for in-memory computing,” IEEE International Electron Devices Meeting (IEDM) 2021, San Francisco, USA.
  85. K. A. Aabrar, J. Gomez, S. G. Kirtania, M. San Jose, Y. Luo, P. G. Ravikumar, P. V. Ravindran, H. Ye, S. Banerjee, S. Dutta, A. I. Khan, S. Yu, S. Datta, “BEOL compatible superlattice FerroFET-based high precision analog weight cell with superior linearity and symmetry,” IEEE International Electron Devices Meeting (IEDM) 2021, San Francisco, USA.
  86. Z. Lin, M. Si, Y.-C. Luo, X. Lyu, A. Charnas, Z. Chen, Z. Yu, W. Tsai, P. C. McIntyre, R. Kanjolia, M. Moinpour, S. Yu, P. D. Ye, “High-performance BEOL-compatible atomic-layer-deposited In2O3 Fe-FETs enabled by channel length scaling down to 7 nm: Achieving performance enhancement with large memory window of 2.2 V, long retention > 10 years and high endurance > 108 cycles,” IEEE International Electron Devices Meeting (IEDM) 2021, San Francisco, USA.
  87. N. Tasneem, Z. Wang, Z. Zhao, N. Upadhyay, S. Lombardo, H. Chen, J. Hur, D. Triyoso, S. Consiglio, K. Tapily, R. Clark, G. Leusink, S. Kurinec, S. Datta, S. Yu, K. Ni, M. Passlack, W. Chern, A. I. Khan, “Trap capture and emission dynamics in ferroelectric field-effect transistors and their impact on device operation and reliability,” IEEE International Electron Devices Meeting (IEDM) 2021, San Francisco, USA.
  88. Z. Wang, N. Tasneem, J. Hur, H. Chen, S. Yu, W. Chern, A. I. Khan, “Standby bias improvement of read after write delay in ferroelectric field effect transistors,” IEEE International Electron Devices Meeting (IEDM) 2021, San Francisco, USA.
  89. S. Yu, W. Shim, J. Hur, Y.-C. Luo, G. Choe, W. Li, A. Lu, X. Peng, “Compute-in-memory: from device innovation to 3D system integration,” IEEE European Solid-State Device Research Conference (ESSDERC) 2021, virtual, invited keynote.
  90. W. Li, X. Sun, H. Jiang, S. Huang, S. Yu, “A 40nm RRAM compute-in-memory macro featuring on-chip write-verify and offset-cancelling ADC references,” IEEE European Solid-State Circuits Conference (ESSCIRC) 2021, virtual.
  91. W. Li, S. Huang, X. Sun, H. Jiang, S. Yu, “Secure-RRAM: A 40nm 16kb compute-in-memory macro with reconfigurability, sparsity control, and embedded security,” IEEE Custom Integrated Circuits Conference (CICC) 2021, virtual.
  92. Y. Luo, Y.-C. Luo, S. Yu, “A FeRAM based volatile/non-volatile dual-mode buffer memory for deep neural network training,” ACM/IEEE Design, Automation & Test in Europe (DATE) 2021, virtual.
  93. A. Lu, X. Peng, Y. Luo, S. Huang, S. Yu, “A runtime reconfigurable design of compute-in-memory based hardware accelerator,” ACM/IEEE Design, Automation & Test in Europe (DATE) 2021, virtual.
  94. P. Wang, X. Peng, W. Chakraborty, A. I. Khan, S. Datta, S. Yu, “Cryogenic performance for compute-in-memory based deep neural network accelerator,” IEEE International Symposium on Circuits and Systems (ISCAS) 2021, virtual.
  95. S. Huang, X. Peng, H. Jiang, Y. Luo, S. Yu, “Exploiting process variations to protect machine learning inference engine from chip cloning,” IEEE International Symposium on Circuits and Systems (ISCAS) 2021, virtual.
  96. A. Lu, X. Peng, W. Li, H. Jiang, S. Yu, “NeuroSim validation with 40nm RRAM compute-in-memory macro,” IEEE International Conference on Artificial Intelligence Circuits & Systems (AICAS) 2021, virtual.
  97. A. Lu, X. Peng, S. Yu, “Compute-in-RRAM with limited on-chip resources,” IEEE International Conference on Artificial Intelligence Circuits & Systems (AICAS) 2021, virtual.
  98. S. Huang, H. Jiang, S. Yu, “Mitigating adversarial attack for compute-in-memory accelerator utilizing on-chip finetune,” IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA) 2021, virtual.
  99. W. Shim, J. Meng, X. Peng, J.-S. Seo, S. Yu, “Impact of multilevel retention characteristics on RRAM based DNN inference engine,” IEEE International Reliability Physics Symposium (IRPS) 2021, virtual.
  100. W. He, W. Shim, S. Yin, X. Sun, D. Fan, S. Yu, J.-S. Seo, “Characterization and mitigation of relaxation effects on multi-level RRAM based in-memory computing,” IEEE International Reliability Physics Symposium (IRPS) 2021, virtual (nomination for the best student paper).
  101. Y.-C. Luo, S. Datta, S. Yu, “Three-dimensional (3D) non-volatile SRAM with IWO transistor and HZO ferroelectric capacitor,” IEEE International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2021, virtual.
  102. Y.-C. Luo, A. Lu, J. Hur, S. Li, S. Yu, “Design of non-volatile capacitive crossbar array for in-memory computing,” IEEE International Memory Workshop (IMW) 2021, virtual.
  103. J. Hur, Y.-C. Luo, Z. Wang, W. Shim, A. I. Khan, S. Yu, “A technology path for scaling embedded FeRAM to 28nm with 2T1C structure,” IEEE International Memory Workshop (IMW) 2021, virtual.
  104. G. Choe, S. Yu, “Variability analysis for ferroelectric field-effect transistors,” IEEE Electron Devices Technology and Manufacturing Conference (EDTM) 2021, virtual.
  105. G. Choe, S. Yu, “Advanced gate stack design of ferroelectric transistor for scaling towards 7nm FinFET platform,” IEEE Silicon Nanoelectronics Workshop (SNW) 2021, virtual.
  106. G. Choe, J. Hur, S. Yu, “Scaling FeFET towards 7nm node: A TCAD perspective,” Materials Research Society (MRS) Spring Meeting 2021, virtual.
  107. W. Li, S. Yu, “A 40nm RRAM compute-in-memory macro,” IBM AI Hardware Forum 2021, virtual.
  108. B. Lin, G. Choe, J. Hur, A. I. Khan, S. Yu, H. Wang, “Experimental RF characterization of ferroelectric hafnium zirconium oxide material at GHz for microwave applications,” IEEE Device Research Conference (DRC) 2021, virtual.
  109. A. Kaul, Y. Luo, X. Peng, S. Yu, M. S. Bakir, “Thermal reliability considerations of resistive synaptic devices for 3D CIM system performance,” IEEE International Conference on 3D System Integration (3DIC) 2021, Raleigh, NC, USA.
  110. X. Sun, W. Li, H. Jiang, S. Yu, “A 40nm RRAM-based flexible precision compute-in-memory macro,” Government Microcircuit Applications and Critical Technology Conference (GOMACTech) 2021, virtual.
  111. J. Sacane, X. Han, H. Barnaby, S. Yu, “Total ionizing dose effect on HfO2 RRAM array and its impact on neural networks,” Government Microcircuit Applications and Critical Technology Conference (GOMACTech) 2021, virtual.
  112. S. Huang, H. Jiang, S. Yu, “Mitigating adversarial attack for compute-in-memory accelerator utilizing on-chip finetune,” Government Microcircuit Applications and Critical Technology Conference (GOMACTech) 2021, virtual.
  113. X. Peng, W. Chakraborty, A. Kaul, W. Shim, M. S. Bakir, S. Datta, S. Yu, “Benchmarking monolithic 3D integration for compute-in-memory accelerators: overcoming ADC bottlenecks and maintaining scalability to 7nm or beyond,” IEEE International Electron Devices Meeting (IEDM) 2020, virtual.
  114. P. Wang, X. Peng, W. Chakraborty, A. I. Khan, S. Datta, S. Yu, “Cryogenic benchmarks of embedded memory technologies for recurrent neural network based quantum error correction,” IEEE International Electron Devices Meeting (IEDM) 2020, virtual.
  115. J. Hur, P. Wang, Z. Wang, G. Choe, N. Tasneem, A. I. Khan, S. Yu, “Interplay of switching characteristics, cycling endurance and multilevel retention of ferroelectric capacitor,” IEEE International Electron Devices Meeting (IEDM) 2020, virtual.
  116. S. Dutta, H. Ye, W. Chakraborty, Y.-C. Luo, M. San Jose, B. Grisafe, A. Khanna, I. Lightcap, S. Shinde, S. Yu, S. Datta, “Monolithic 3D integration of high endurance multi-bit ferroelectric FET for accelerating compute-in-memory,” IEEE International Electron Devices Meeting (IEDM) 2020, virtual.
  117. Z. Wang, M. M. Islam, P. Wang, S. Deng, S. Yu, A. I. Khan, K. Ni, “Depolarization field induced instability of polarization states in HfO2 based ferroelectric FET,” IEEE International Electron Devices Meeting (IEDM) 2020, virtual.
  118. A. Kaul, X. Peng, S. K. Raja, S. Yu, M. S. Bakir, “Thermal modeling of 3D polylithic integration and implications on BEOL RRAM performance, IEEE International Electron Devices Meeting (IEDM) 2020, virtual, invited.
  119. J-W. Su, X. Si, Y-C. Chou, T-W. Chang, W-H. Huang, Y-N. Tu, R. Liu, P-J. Lu, T-W. Liu, J-H. Wang, Z. Zhang, H. Jiang, S. Huang, S. Yu, K-T. Tang, C-C. Hsieh, R-S. Liu, S-H. Li, S-S. Sheu, H-Y. Lee, S-C. Chang, M-F. Chang, “A 28nm 64Kb inference-training two-way transpose multibit 6T SRAM computing-in-memory macro for AI edge chips” IEEE International Solid-State Circuits Conference (ISSCC) 2020, San Francisco, USA.
  120. H. Jiang, S. Huang, X. Peng, J.-W. Su, Y.-C. Chou, W.-H. Huang, T.-W. Liu, R. Liu, M.-F. Chang, S. Yu, “A two-way SRAM array based accelerator for deep neural network on-chip training,” ACM/IEEE Design Automation Conference (DAC) 2020, virtual (nomination for the best paper).
  121. S. Yu, X. Sun, X. Peng, S. Huang, “Compute-in-memory with emerging nonvolatile-memories: challenges and prospects,” IEEE Custom Integrated Circuits Conference (CICC) 2020, virtual, invited.
  122. S. Huang, X. Sun, X. Peng, H. Jiang, S. Yu, “Overcoming challenges for achieving high in-situ training accuracy with emerging memories,” ACM/IEEE Design, Automation & Test in Europe (DATE) 2020, virtual, invited.
  123. S. Huang, H. Jiang, X. Peng, W. Li, S. Yu, “XOR-CIM: Compute-in-memory SRAM architecture with embedded XOR encryption,” ACM/IEEE International Conference on Computer-Aided Design (ICCAD) 2020, virtual.
  124. Y. Luo, S. Yu, “Benchmark non-volatile and volatile memory-based hybrid precision synapses for in-situ deep neural network training,” ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) 2020, Beijing, China, invited.
  125. W. Shim, Y. Luo, J.-S. Seo, S. Yu, “Impact of read disturb on multilevel RRAM based inference engine: experiments and model prediction,” IEEE International Reliability Physics Symposium (IRPS) 2020, virtual.
  126. W. Shim, H. Jiang, X. Peng, S. Yu, “Architectural design of 3D NAND Flash based compute-in-memory for inference engine,” ACM/IEEE International Symposium on Memory Systems (MEMSYS) 2020, virtual.
  127. H. Jiang, X. Peng, S. Huang, S. Yu, “MINT: Mixed-precision RRAM-based in-memory training architecture,” IEEE International Symposium on Circuits and Systems (ISCAS) 2020, virtual.
  128. Y. Luo, X. Peng, R. Hatcher, T. Rakshit, J. Kittl, M. S. Rodder, J.-S. Seo, S. Yu, “A variation robust inference engine based on STT-MRAM with parallel read-out,” IEEE International Symposium on Circuits and Systems (ISCAS) 2020, virtual.
  129. H. Jiang, R. Liu, S. Yu, “8T XNOR-SRAM based parallel compute-in-memory for deep neural network accelerator,” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) 2020, virtual, invited.
  130. Y.-C. Luo, J. Hur, P. Wang, A. I. Khan, S. Yu, “Modeling multi-states in ferroelectric tunnel junction,” IEEE Device Research Conference (DRC) 2020, virtual.
  131. S. Yu, P. Wang, “Ferroelectric devices for compute-in-memory: array-level operations” IEEE Device Research Conference (DRC) 2020, virtual, invited.
  132. J. Hur, Y.-C. Luo, P. Wang, N. Tasneem, A. I. Khan, S. Yu, “Ferroelectric tunnel junction optimization by plasma-enhanced atomic layer deposition,” IEEE Silicon Nanoelectronics Workshop (SNW) 2020, virtual.
  133. G. Choe, W. Shim, J. Hur, A. I. Khan, S. Yu, “Impact of random phase distribution in 3D vertical NAND architecture of ferroelectric transistors on in-memory computing,” IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 2020, virtual.
  134. S. Yu, P. Wang, X. Peng, “Ferroelectric transistors for synaptic devices: challenges and prospects,” IEEE International Conference on Solid-State and Integrated Circuits Technology (ICSICT) 2020, virtual, invited.
  135. S. Huang, H. Jiang, S. Yu, “Mitigating adversarial attack for compute-in-memory accelerator utilizing on-chip finetune,” IBM AI Compute Symposium 2020, virtual.
  136. X. Han, A. Privat, K. E. Holbert, J.-S. Seo, S. Yu, H. J. Barnaby, “Total ionizing dose effect on multi-state HfOx-based RRAM synaptic array,” IEEE Nuclear & Space Radiation Effects Conference (NSREC) 2020, virtual.
  137. X. Peng, S. Huang, Y. Luo, X. Sun, S. Yu, “DNN+NeuroSim: An end-to-end benchmarking framework for compute-in-memory accelerators with versatile device technologies,” IEEE International Electron Devices Meeting (IEDM) 2019, San Francisco, USA.
  138. M. Si, Y. Luo, W. Chung, H. Bae, D. Zheng, J. Li, J. Qin, G. Qiu, S. Yu, P. D. Ye, “A novel scalable energy-efficient synaptic device: crossbar ferroelectric semiconductor junction,” IEEE International Electron Devices Meeting (IEDM) 2019, San Francisco, USA.
  139. X. Si, J.-J. Chen, Y.-N. Tu, W.-H. Huang, J.-H. Wang, W.-C. Wei, S.-Y. Wu, X. Sun, R. Liu, S. Yu, R.-S. Liu, C.-C. Hsieh, K.-T. Tang, Q. Li, M.-F. Chang, “A twin-8T SRAM computation-in-memory macro for multiple-bit CNN-based machine learning,” IEEE International Solid-State Circuits Conference (ISSCC) 2019, San Francisco, USA.
  140. Y. Pang, B. Gao, D. Wu, S. Yi, Q. Liu, W.-H. Chen, T.-W. Chang, W.-E. Lin, X. Sun, S. Yu, H. Qian, M.-F. Chang, H. Wu, “A reconfigurable RRAM physically unclonable function utilizing post-process randomness source with <6×10-6 native bit error rate,” IEEE International Solid-State Circuits Conference (ISSCC) 2019, San Francisco, USA.
  141. H. Jiang, X. Peng, S. Huang,  S. Yu, “CIMAT: A transpose SRAM-based compute-in-memory architecture for deep neural network on-chip training,” ACM/IEEE International Symposium on Memory Systems (MEMSYS) 2019, Washington, DC, USA.
  142. X. Peng, M. Kim, X. Sun, S. Yin, T. Rakshit, R. M. Hatcher, J. A. Kittl, J.-S. Seo, S. Yu, “Inference engine benchmarking across technological platforms from CMOS to post-CMOS,” ACM/IEEE International Symposium on Memory Systems (MEMSYS) 2019, Washington, DC, USA.
  143. X. Peng, R. Liu, S. Yu, “Optimizing weight mapping and data flow for convolutional neural networks on RRAM based processing-in-memory architecture,” IEEE International Symposium on Circuits and Systems (ISCAS) 2019, Sapporo, Japan.
  144. J. Woo, S. Yu, “Design space exploration of Ovonic Threshold Switch (OTS) for sub-threshold read operation in cross-point memory arrays,” IEEE International Symposium on Circuits and Systems (ISCAS) 2019, Sapporo, Japan.
  145. Y. Luo, X. Peng, S. Yu, “MLP+NeuroSimV3.0: Improving on-chip learning performance with device to algorithm optimizations,” International Conference on Neuromorphic Systems (ICONS) 2019, Knoxville, TN, USA.
  146. P. Wang, Z. Wang, N. Tasneem, J. Hur, A. I. Khan, S. Yu, “Investigating hysteresis minor loop of ferroelectric capacitor,” IEEE Non-Volatile Memory Technology Symposium (NVMTS) 2019, Durham, NC, USA.
  147. Z. Ye, H. Barnaby, S. Yu, “Evaluation of single event effects in SRAM and RRAM based neuromorphic computing system,” IEEE International Reliability Physics Symposium (IRPS) 2019, Monterey, CA, USA.
  148. J. Woo, S. Yu, “Device design and material considerations of Ovonic Threshold Switch (OTS) for cross-point MRAM array,” IEEE Electron Devices Technology and Manufacturing Conference (EDTM) 2019, Singapore.
  149. J. Woo, S. Yu, “Device and material considerations of Ovonic Threshold Switch (OTS) for cross-point memory technology,” Materials Research Society (MRS) Spring Meeting 2019, Phoenix, USA, invited.
  150. H. Jiang, X. Peng, S. Huang, S. Yu, “CIMAT: A transpose SRAM-based compute-in-memory architecture for deep neural network on-chip training,” Workshop on Hardware and Algorithms for Learning On-a-chip (HALO) 2019, Denver, CO.
  151. R. Islam, H. Li, P.-Y. Chen, W. Wan, H.-Y. Chen, B. Gao, H. Wu, S. Yu, K. Saraswat, H.-S. P. Wong, “Device and materials requirements for neuromorphic computing,” Materials Research Society (MRS) Spring Meeting 2019, Phoenix, USA, invited.
  152. W. Zhang, X. Peng, H. Wu, B. Gao, S. Yu, Y. Zhang, H. He, H. Qian, “Design guidelines of RRAM based neural-processing-unit: a joint device-circuit-algorithm analysis,” ACM/IEEE Design Automation Conference (DAC) 2019, Las Vegas, USA.
  153. M. Jerry, S. Dutta, A. Kazemi, K. Ni, J. Zhang, P.-Y. Chen, P. Sharma, S. Yu, X. S. Hu, M. Niemier, S. Datta, “Ferroelectric FET based non-volatile analog synaptic weight cell”, Government Microcircuit Applications and Critical Technology Conference (GOMACTech) 2019, Albuquerque, NM.
  154. X. Sun, P. Wang, K. Ni, S. Datta, S. Yu, “Exploiting hybrid precision for training and inference: a 2T-1FeFET based analog synaptic weight cell,” IEEE International Electron Devices Meeting (IEDM) 2018, San Francisco, USA (highlight paper and nominated for the best student paper).
  155. N. Xu, F. Chen, Y. Lu, W. Qi, X. Peng, Z. Jiang, J. Wang, W. Choi, S. Yu, D. S. Kim, “STT-MRAM design technology co-optimization for hardware neural networks,” IEEE International Electron Devices Meeting (IEDM) 2018, San Francisco, USA.
  156. M. Zhao, H. Wu, B. Gao, X. Sun, Y. Liu, P. Yao, Y. Xi, X. Li, K. Wang, S. Yu, H. Qian, “Characterizing endurance degradation of incremental switching in analog RRAM for neuromorphic systems,” IEEE International Electron Devices Meeting (IEDM) 2018, San Francisco, USA.
  157. Y. Lin, H. Wu, B. Gao, P. Yao, W. Wu, G. Li, S. Yu, H. Qian, “Demonstration of generative adversarial network by intrinsic random noises of analog RRAM devices,” IEEE International Electron Devices Meeting (IEDM) 2018, San Francisco, USA.
  158. W.-S. Khwa, J.-J. Chen, J.-F. Li, X. Si, E.-Y. Yang, X. Sun, R. Liu, P.-Y. Chen, Q. Li, S. Yu, M.-F. Chang, “A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors,” IEEE International Solid-State Circuits Conference (ISSCC) 2018, San Francisco, USA.
  159. R. Liu, X. Peng, X. Sun, W.-S. Khwa, X. Si, J.-J. Chen, J.-F. Li, M.-F. Chang, S. Yu, “Parallelizing SRAM arrays with customized bit-cell for binary neural networks,” ACM/IEEE Design Automation Conference (DAC) 2018, San Francisco, USA (nominated for best student paper).
  160. X. Sun, S. Yin, X. Peng, R. Liu, J.-S. Seo, S. Yu, “XNOR-RRAM: A scalable and parallel synaptic architecture for binary neural networks,” ACM/IEEE Design, Automation & Test in Europe (DATE) 2018, Dresden, Germany.
  161. X. Sun, X. Peng, P.-Y. Chen, R. Liu, J.-S. Seo, S. Yu, “Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons,” ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) 2018, Jeju Island, Korea.
  162. P.-Y. Chen, S. Yu, “Reliability perspective of resistive synaptic devices on the neuromorphic system performance,” IEEE International Reliability Physics Symposium (IRPS) 2018, San Francisco, USA, invited.
  163. J. Woo, X. Peng, S. Yu, “Design considerations of selector device in cross-point RRAM array for neuromorphic computing,” IEEE International Symposium on Circuits and Systems (ISCAS) 2018, Florence, Italy.
  164. X. Sun, R. Liu, X. Peng, S. Yu, “Computing-in-memory with SRAM and RRAM for binary neural networks,” IEEE International Conference on Solid-State and Integrated Circuits Technology (ICSICT) 2018, Qingdao, China, invited.
  165. X. Peng, S. Yu, “Benchmark of RRAM based architectures for dot-product computation,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) 2018, Chengdu, China, invited.
  166. Z. Ye, R. Liu, J. Taggart, H. Barnaby, S. Yu, “Evaluation of radiation effects in RRAM based neuromorphic computing system,” IEEE Nuclear and Space Radiation Effects Conference (NSREC) 2018, Hawaii, USA.
  167. M. Mao, X. Sun, X. Peng, S. Yu, C. Chakrabarti, “A versatile ReRAM-based accelerator for convolutional neural networks,” IEEE Workshop on Signal Processing Systems (SiPS) 2018, Cape Town, South Africa.
  168. S. Yin, X. Sun, S. Yu, J.-S. Seo, C. Chakrabarti, “A parallel RRAM synaptic array architecture for energy-efficient recurrent neural networks,” IEEE Workshop on Signal Processing Systems (SiPS) 2018, Cape Town, South Africa.
  169. W. Wu, H. Wu, B. Gao, P. Yao, X. Zhang, X. Peng, S. Yu, He Qian, “A methodology to improve linearity of analog RRAM for neuromorphic computing,” IEEE Symposium on VLSI Technology (VLSI) 2018, Hawaii, USA.
  170. P.-Y. Chen, X. Peng, S. Yu, “NeuroSim+: An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures,” IEEE International Electron Devices Meeting (IEDM) 2017, San Francisco, USA.
  171. M. Jerry, P.-Y. Chen, J. Zhang, P. Sharma, K. Ni, S. Yu, S. Datta, “Ferroelectric FET analog synapse for acceleration of deep neural network training,” IEEE International Electron Devices Meeting (IEDM) 2017, San Francisco, USA.
  172. A. Mohanty, X. Du, P.-Y. Chen, J.-S. Seo, S. Yu, Y. Cao, “Random sparse adaptation for accurate inference with inaccurate multi-level RRAM arrays,” IEEE International Electron Devices Meeting (IEDM) 2017, San Francisco, USA.
  173. B. Gao, H. Wu, W. Wu, X. Wang, P. Yao, Y. Xi, W. Zhang, N. Deng, P. Huang, X. Y. Liu, J. F. Kang, H.-Y. Chen, S. Yu, H. Qian, “Modeling disorder effect of the oxygen vacancy distribution in filamentary analog RRAM for neuromorphic computing,” IEEE International Electron Devices Meeting (IEDM) 2017, San Francisco, USA.
  174. M. Zhao, H. Wu, B. Gao, Q. Zhang, W. Wu, S. Wang, Y. Xi, D. Wu, N. Deng, S. Yu, H.-Y. Chen, H. Qian, “Investigation of statistical retention of filamentary analog RRAM for neuromophic computing,” IEEE International Electron Devices Meeting (IEDM) 2017, San Francisco, USA.
  175. H. Wu, P. Yao, B. Gao, W. Wu, Q. Zhang, W. Zhang, N. Deng, D. Wu, H.-S. P. Wong, S. Yu, H. Qian, “’Device and circuit optimization of RRAM for neuromorphic computing, IEEE International Electron Devices Meeting (IEDM) 2017, San Francisco, USA, invited.
  176. R. Liu, H.-Y. Lee, S. Yu, “Analyzing inference robustness of RRAM synaptic array in low-precision neural network,” IEEE European Solid-State Device Research Conference (ESSDERC) 2017, Leuven, Belgium.
  177. P.-Y. Chen, X. Peng, S. Yu, “System-level benchmark of synaptic device characteristics for neuro-inspired computing,” IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) 2017, San Francisco, USA, invited.
  178. R. Liu, H. Wu, Y. Pang, H. Qian, S. Yu, “Extending 1kb RRAM array from weak PUF to strong PUF by employment of SHA module,” IEEE Asian Hardware-Oriented Security and Trust Symposium (AsianHOST) 2017, Beijing, China.
  179. R. Liu, P.-Y. Chen, S. Yu, “Design and optimization of a strong PUF exploiting sneak paths in resistive cross-point Array,” IEEE International Symposium on Circuits and Systems (ISCAS) 2017, Baltimore, USA.
  180. L. Gao, P.-Y. Chen, S. Yu, “Exploiting NbOx metal-insulator-transition device as oscillation neuron for neuro-inspired computing,” IEEE Electron Devices Technology and Manufacturing (EDTM) 2017, Toyama, Japan.
  181. S. Yu, L. Gao, B. Dong, P.-Y. Chen, “Oscillation neuron device design considerations,” Materials Research Society (MRS) Spring Meeting 2017, Phoenix, USA, invited.
  182. A. Tosson, S. Yu, M. H. Anis, L. Wei, “Mitigating the effect of reliability soft-errors of RRAM devices on the performance of RRAM-based neuromorphic systems,” ACM Great Lakes Symposium on VLSI (GLSVLSI) 2017, Banff, Alberta, Canada.
  183. A. Tosson, S. Yu, M. H. Anis, L. Wei, “Analysis of RRAM reliability soft-errors on the performance of RRAM-based neuromorphic systems,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2017, Bochum, Germany.
  184. A. Tosson, S. Yu, M. H. Anis, L. Wei, “1T2R: a novel memory cell design to resolve single-event upset in RRAM arrays,” IEEE International Conference on ASIC (ASICON) 2017, Guiyang, China.
  185. P. Yao, H. Wu, B. Gao, N. Deng, S. Yu, H. Qian, “Online training on RRAM based neuromorphic network: experimental demonstration and operation scheme optimization,” IEEE Electron Devices Technology and Manufacturing (EDTM) 2017, Toyama, Japan.
  186. Y. Pang, H. Wu, B. Gao, R. Liu, S. Wang, S. Yu, A. Chen, H. Qian, “Design and optimization of strong physical unclonable function (PUF) based on RRAM array,” IEEE International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2017, Hsinchu, Taiwan.
  187. S. Yu, Z. Li, P.-Y. Chen, H. Wu, B. Gao, D. Wang, W. Wu, H. Qian, “Binary neural network with 16 Mb RRAM macro chip for classification and online training,” IEEE International Electron Devices Meeting (IEDM) 2016, San Francisco, USA. 
  188. P.-Y. Chen, J.-S. Seo, Y. Cao, S. Yu, “Compact oscillation neuron exploiting metal-
    insulator-transition for neuromorphic computing,” ACM/IEEE International Conference on Computer-Aided Design (ICCAD) 2016, Austin, TX, USA.
  189. L. Gao, P.-Y. Chen, S. Yu, “Weight tuning of resistive memories and convolution kernel operation on cross-point array for neuro-inspired computing,” IEEE International Conference on Solid-State and Integrated Circuits Technology (ICSICT) 2016, Hangzhou, China, invited.
  190. R. Liu, H. Wu, Y. Pang, H. Qian, S. Yu, “A highly reliable and tamper-resistant RRAM PUF: design and experimental validation,” IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) 2016, Washington DC, USA.
  191. P.-Y. Chen, S. Yu, “Partition SRAM and RRAM based synaptic arrays for neuro-inspired computing,” IEEE International Symposium on Circuits and Systems (ISCAS) 2016, Montreal, Canada.
  192. A. Shrivastava, P.-Y. Chen, Y. Cao, S. Yu, C. Chakrabarti, “Design of a reliable RRAM-based PUF for compact hardware security primitives,” IEEE International Symposium on Circuits and Systems (ISCAS) 2016, Montreal, Canada.
  193. Z. Xu, P.-Y. Chen, J.-S. Seo, S. Yu, Y. Cao, “Hardware-efficient learning with feedforward inhibition,” IEEE Nanoelectronics Conference (INEC) 2016, Chengdu, China, invited.
  194. L. Xia, B. Li, T. Tang, P. Gu, X. Yin, W. Huangfu, P.-Y. Chen, S. Yu, Y. Cao, Y. Wang, Y. Xie, H. Yang, “MNSIM: simulation platform for memristor-based neuromorphic computing system,” IEEE Design, Automation & Test in Europe (DATE) 2016, Dresden, Germany.
  195. Y. Cao, S. Yu, Y. Wang, P.-Y. Chen, L. Xia, H. Yang, “Neuromorphic computing with resistive synaptic arrays: devices, circuits and systems,” IEEE International Symposium on Quality Electronic Design (ISQED) 2016, Santa Clara, CA, USA, invited.
  196. Y. Cao, S. Skorheim, M. Tu, P.-Y. Chen, S. Yu, J.-S. Seo, V. Berisha, M. Bazhenov, Z. Xu, “Efficient neuromorphic learning with motifs of feedforward inhibition,” Neuromorphic Computing Workshop at Oak Ridge National Laboratory 2016, Knoxville, TN.
  197. R. Karam, R. Liu, P.-Y. Chen, S. Yu, and S. Bhunia, “Security primitive design with nanoscale devices: a case study with resistive RAM,” ACM Great Lakes Symposium on VLSI (GLSVLSI) 2016, Boston, USA, invited.
  198. L. Ceze, J. Hasler, K. K. Likharev, J.-S. Seo, T. Sherwood, D. Strukov, Y. Xie, S. Yu, “Nanoelectronic neurocomputing: status and prospects,” IEEE Device Research Conference (DRC) 2016, Newark, DE, USA, invited.
  199. S. Yu, P.-Y. Chen, Y. Cao, L. Xia, Y. Wang, H. Wu, “Scaling-up resistive synaptic arrays for neuro-inspired architecture: challenges and prospect,” IEEE International Electron Devices Meeting (IEDM) 2015, Washington DC, USA, invited. 
  200. S. B. Eryilmaz, D. Kuzum, S. Yu, H.-S. P. Wong, “Device and system level design considerations for analog-non-volatile-memory based neuromorphic architectures,” IEEE International Electron Devices Meeting (IEDM) 2015, Washington DC, USA, invited. 
  201. P.-Y. Chen, B. Lin, I.-T. Wang, T.-H. Hou, J. Ye, S. Vrudhula, J.-S. Seo, Y. Cao, and S. Yu, “Mitigating effects of non-ideal synaptic device characteristics for on-chip learning,” ACM/IEEE International Conference on Computer-Aided Design (ICCAD) 2015, Austin, TX, USA. 
  202. L. Gao, S. Yu, “Programming protocol optimization for analog weight tuning in resistive memories,” IEEE Device Research Conference (DRC) 2015, Columbus, OH, USA.
  203. R. Fang, W. Chen, L. Gao, S. Yu, “Low temperature characteristics of HfOx-based resistive random access memory,” MRS Electronic Materials Conference (EMC) 2015, Columbus, OH, USA. 
  204. P.-Y. Chen, D. Kadetotad, Z. Xu, A. Mohanty, B. Lin, J. Ye, S. Vrudhula, J.-S. Seo, Y. Cao, S. Yu, “Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip,” IEEE Design, Automation & Test in Europe (DATE) 2015, Grenoble, France.
  205. P.-Y. Chen, R. Fang, R. Liu, C. Chakrabarti, Y. Cao, S. Yu, “Exploiting resistive cross-point array for compact design of physical unclonable function,” IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) 2015, Washington DC, USA.
  206. S. Zuloaga, R. Liu, P.-Y. Chen, and S. Yu, “Scaling 2-layer RRAM cross-point array towards 10 nm node: a device-circuit co-design, IEEE International Symposium on Circuits and Systems (ISCAS) 2015, Lisbon, Portugal.
  207. S. Yu, Y. Cao, “On-chip sparse learning with resistive cross-point array architecture,” ACM Great Lakes Symposium on VLSI (GLSVLSI) 2015, Pittsburgh, USA, invited.
  208. P.-Y. Chen, S. Yu, “NeuroSim: A circuit-level benchmark simulator for neuro-inspired architectures,” Workshop on Hardware and Algorithms for Learning On-a-chip (HALO) 2015, Austin, TX.
  209. Z. Xu, S. Skorheim, M. Bazhenov, J.-S. Seo, S. Yu, Y. Cao, “Sparse learning with reward, habituation, inhibition and noise,” Workshop on Hardware and Algorithms for Learning On-a-chip (HALO) 2015, Austin, TX.
  210. M. Mao, Y. Cao, S. Yu, and C. Chakrabarti, “Optimizing latency, energy, and reliability of 1T1R ReRAM through appropriate voltage settings,” IEEE International Conference on Computer Design (ICCD) 2015, New York, USA.
  211. M. Mao, Y. Cao, S. Yu, and C. Chakrabarti, “Programming strategies to improve energy efficiency and reliability of ReRAM memory systems,” IEEE Workshop on Signal Processing Systems (SiPS) 2015, Hangzhou, China.
  212. W. Chen, H. J. Barnaby, M. N. Kozicki, Y. Gonzalez-Velo, R. Fang, K. Holbert, S. Yu, W. Yu, “A study of gamma-ray exposure of Cu-SiO2 programmable metallization cells,” IEEE Nuclear and Space Radiation Effects Conference (NSREC) 2015, Boston, USA.
  213. P. Gu, B. Li, T. Tang, S. Yu, Y. Cao, Y. Wang, H. Yang, “Technological exploration of RRAM crossbar array for matrix-vector multiplication,” Asia and South Pacific Design Automation Conference (ASP-DAC) 2015, Tokyo, Japan.
  214. C. Xu, D. Niu, N. Muralimanohar, R. Balasubramonian, T. Zhang, S. Yu, Y. Xie, “Overcoming the challenges of cross-point resistive memory architectures,” IEEE International Symposium on High Performance Computer Architecture (HPCA) 2015, San Francisco, USA. 
  215. C. Xu, D. Niu, N. Muralimanohar, R. Balasubramonian, T. Zhang, S. Yu, Y. Xie, “Design a high-performance main memory by overcoming the challenges of crossbar resistive memory architectures,” 6th Annual Non-Volatile Memories Workshop (NVMW) 2015, San Diego, USA.
  216. Z. Jiang, P. Huang, L. Zhao, S. Kvatinsky, S. Yu, X. Y. Liu, J. F. Kang, Y. Nishi, and H. -S. P. Wong, “Performance prediction of large-scale 1S1R resistive memory array using machine learning,” IEEE International Memory Workshop (IMW) 2015, Monterey, CA, USA.
  217. J. F. Kang, B. Gao, P. Huang, L. F. Liu, X. Y. Liu, S. Yu, H. Y. Yu, H.-S. P. Wong, “RRAM based synaptic devices for neuromorphic visual systems,” IEEE International Conference on Digital Signal Processing (DSP) 2015, Singapore, invited.
  218. P.-Y. Chen, and S. Yu, “Impact of vertical RRAM device characteristics on 3D cross-point array design,” IEEE International Memory Workshop (IMW) 2014, pp.127-130, Taipei, Taiwan.
  219. P.-Y. Chen, and S. Yu, “Design of heterojunction oxide stack for 3D RRAM cross-point array,” 5th Annual Non-Volatile Memories Workshop (NVMW) 2014, San Diego, USA.
  220. P.-Y. Chen, C. Xu, Y. Xie, and S. Yu, “3D RRAM design and benchmark with 3D NAND FLASH,” IEEE International Conference on Solid-State and Integrated Circuits Technology (ICSICT) 2014, Guilin China, invited.  
  221. J. Yang, N. Kulkarni, S. Yu, and S. Vrudhula, “Integration of threshold logic gates with RRAM devices for energy efficient and robust operation,”  ACM/IEEE International Symposium on Nanoscale Architectures (NANOARCH) 2014, Paris, France.
  222. D. Kadetotad, Z. Xu, A. Mohanty, P.-Y. Chen, B. Lin, J. Ye, S. Vrudhula, S. Yu, Y. Cao, J.-S. Seo, “Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning,” IEEE Biomedical Circuits and Systems Conference (Bio-CAS) 2014, Lausanne, Switzerland.
  223. C. Xu, P.-Y. Chen, D. Niu, Y. Zheng, S. Yu, and Y. Xie,  “Architecting 3D vertical resistive memory for next-generation storage systems,” International Conference on Computer-Aided Design (ICCAD) 2014, San Jose, USA.
  224. C. Xu, D. Niu, Y. Zheng, S. Yu, and Y. Xie, “Reliability-aware cross-point resistive memory design,” ACM Great Lakes Symposium on VLSI (GLSVLSI) 2014, pp. 145-150, Houston, USA.
  225. C. Xu, D. Niu, S. Yu, and Y. Xie, “Modeling and design analysis of 3D vertical resistive memory- a low cost cross-point architecture,” Asia and South Pacific Design Automation Conference (ASP-DAC) 2014, pp. 825-830, Singapore.
  226. H.-Y Chen, B. Gao, H. Li, R. Liu, P. Huang, Z. Chen, B. Chen, F. Zhang, L. Zhao, Z. Jiang, L. F. Liu, X. Y. Liu, J. F. Kang, S. Yu, Y. Nishi, and H.-S. P. Wong, “Towards high-speed, write-disturb tolerant 3D vertical RRAM arrays,” Symposium on VLSI Technology (VLSI) 2014, pp. 196-197, Hawaii, USA.
  227. L. Zhao, H.-Y. Chen, S.-C. Wu, Z. Jiang, S. Yu, T.-H. Hou, H.-S. P. Wong, and Y. Nishi, “Improved multi-level control of RRAM using pulse-train programming,” International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2014, Hsinchu, Taiwan.
  228. R. Liu, H.-Y. Chen, H. Li, P. Huang, L. Zhao,  Z. Chen, F. Zhang, B. Chen, L. F. Liu, X. Y. Liu, B. Gao, S. Yu, Y. Nishi, H.-S. P. Wong, and J. F. Kang, “Impact of pulse rise time on programming of cross-point RRAM arrays,” International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2014, Hsinchu, Taiwan.
  229. H. Li, H.-Y. Chen, Z. Chen, B. Chen, R. Liu, G. Qiu, P. Huang, F. Zhang, Z. Jiang, B. Gao, L. F. Liu, X. Y. Liu, S. Yu, H.-S. P. Wong, and J. F. Kang, “Write disturb analyses on half-selected cells of cross-point RRAM arrays,” International Reliability Physics Symposium (IRPS), 2014, Waikoloa, HI, USA.
  230. H. Li, Z. Jiang, P. Huang, H.-Y. Chen, B. Chen, R. Liu, Z. Chen, F. Zhang, L. F. Liu, Bi. Gao1, X. Y. Liu, S. Yu, H.-S. P. Wong, and J. F. Kang, “Statistical assessment methodology for the design and optimization of cross-point RRAM arrays,” IEEE International Memory Workshop (IMW) 2014, Taipei, Taiwan.
  231. Z. Jiang, S. Yu, Y. Wu, J. H. Engel, X. Guan, H.-S. P. Wong, “Verilog-A implementation of RRAM compact model for design of selector device,” IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 2014, Yokohama, Japan.
  232. H.-Y. Chen, M. Shulaker, S. Yu, H. Wei, B. Gao, J. Kang, S. Mitra, and H.-S. P. Wong, “Monolithic 3D integration of logic and memory,” 16th ACM/IEEE System Level Interconnect Prediction (SLIP) 2014, San Francisco, USA, invited.
  233. S. Yu, Y. Wu, H.-Y. Chen, Z. Jiang, J. Sohn, H.-S. P. Wong, “Metal–oxide-based resistive switching memory (RRAM): modeling, scaling, and 3D integration,” Materials Research Society (MRS) Spring Meeting  2014, San Francisco, USA, invited. 
  234. S. Yu, “Overview of resistive switching memory (RRAM) switching mechanism and device modeling,” IEEE International Symposium on Circuits and Systems (ISCAS) 2014, Melbourne, Australia, invited.
  235. S. Yu, D. Kuzum, and H.-S. P. Wong, “Design considerations of synaptic device for neuromorphic computing,” IEEE International Symposium on Circuits and Systems (ISCAS) 2014, Melbourne, Australia, invited.
  236. S. Yu, “Orientation classification by a winner-take-all network with oxide RRAM based synaptic devices,” IEEE International Symposium on Circuits and Systems (ISCAS) 2014, Melbourne, Australia, invited.
  237. S. Yu, Y. Deng, B. Gao, P. Huang, B. Chen, X. Y. Liu, J. F. Kang, H.-Y. Chen, Z. Jiang, and H.-S. P. Wong, “Design guidelines for 3D RRAM cross-point architecture,” IEEE International Symposium on Circuits and Systems (ISCAS) 2014, Melbourne, Australia, invited.
  238. J. F. Kang, B. Gao, B. Chen, P. Huang, F. F. Zhang, X. Y. Liu, H.-Y. Chen, Z. Jiang, H.-S. P. Wong, S. Yu, “Scaling and operation characteristics of HfOx based vertical RRAM for 3D cross-point architecture,” IEEE International Symposium on Circuits and Systems (ISCAS) 2014, Melbourne, Australia, invited.
  239. J. F. Kang, B. Gao, Y. J. Bi,  B. Chen, X. Y. Liu, S. Yu, H.-Y. Chen, and H.-S. P. Wong, “TMO-based memristive devices and application for neuromorphic systems,” 13th International Conference on Modern Materials and Technologies (CIMTEC) 2014, Montecantini Terme, Italy, invited.
  240. J. F. Kang, B. Gao, B. Chen, P. Huang1 F. F. Zhang, Y. Deng, L. F. Liu, X. Y. Liu, H.-Y. Chen, Z. Jiang, S. Yu, H.-S. P. Wong, “3D RRAM: design and optimization,” IEEE International Conference on Solid-State and Integrated Circuits Technology (ICSICT) 2014, Guilin, China, invited.
  241. Y. Deng, H.-Y. Chen, B. Gao, S. Yu, S.-C. Wu, L. Zhao, B. Chen, Z. Jiang, X. Y. Liu, T.-H. Hou, Y. Nishi, J. F. Kang, and H.-S. P. Wong, “Design and optimization methodology for 3D RRAM arrays,” IEEE International Electron Devices Meeting (IEDM) 2013,  pp. 629-632, Washington DC, USA. 
  242. S. Yu, and H.-S. P. Wong, “Characterization and modeling of the conduction and switching mechanism of HfOx based RRAM,” Materials Research Society (MRS) Fall Meeting 2013, Boston, USA, invited.
  243. H. Yi, Y. Wu, Z. Zhang, H.-Y. Chen, S. Yu, and H.-S. P. Wong, “Metal oxide resistive switching memory (RRAM): devices, fabrication, and self-assembly patterning for random logic and memory devices (SRAM, NAND, RRAM),” 26th International Microprocesses and Nanotechnology Conference (MNC) 2013, Hokkaido, Japan, invited.
  244. Y. Wu, S. Yu, H.-Y. Chen, J. Liang, Z. Jiang, and H.-S. P. Wong, “Resistive switching random access memory (RRAM): materials, device, scaling, and array design,” 60th International Symposium of the American Vacuum Society (AVS) 2013, Long Beach, CA, USA, invited.
  245. H.-Y. Chen, S. Yu, Y. Wu, and H.-S. P. Wong, “3D vertical RRAM architecture and electrode/oxide interface engineering for next generation mass storage,” International Conference on Solid State Devices and Materials (SSDM) 2013, Fukuoka, Japan, invited.
  246. S. Yu, H.-Y. Chen, Y. Deng, B. Gao, Z. Jiang, J. F. Kang, and H.-S. P. Wong, “3D vertical RRAM – scaling limit analysis and demonstration of 3D array operation,” Symposium on VLSI Technology (VLSI) 2013, pp. 158-159, Kyoto, Japan.
  247. D. Kuzum, R. J. D. Jeyasingh, S. B. Eryilmaz, S. Yu, and H.-S. P. Wong, “Programming phase change synaptic devices for neuromorphic computation,” Materials Research Society (MRS) Spring Meeting 2013, San Francisco, USA, invited.
  248. C.-S. Lee, S. Yu, X. Guan, J. Luo, L. Wei, and H.-S. P. Wong, “Compact models of emerging devices,” IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC) 2013, Hong Kong, invited.
  249. S. Yu, B. Gao, Z. Fang, H. Y. Yu, J. F. Kang, and H.-S. P. Wong, “A neuromorphic visual system using RRAM synaptic devices with sub-pJ energy and tolerance to variability: experimental characterization and large-scale modeling,” IEEE International Electron Devices Meeting (IEDM) 2012, pp. 239-242, San Francisco, USA.
  250. S. Yu, X. Guan, and H.-S. P. Wong, “Understanding metal oxide RRAM current overshoot and reliability using Kinetic Monte Carlo simulation,” IEEE International Electron Devices Meeting (IEDM) 2012, pp. 585-588, San Francisco, USA.
  251. H.-Y. Chen, S. Yu, B. Gao, P. Huang, J. F. Kang, and H.-S. P. Wong, “HfOx based vertical RRAM for cost-effective 3D cross-point architecture without cell selector,” IEEE International Electron Devices Meeting (IEDM) 2012, pp. 497-500, San Francisco, USA.
  252. H.-Y. Chen, H. Tian, B. Gao, S. Yu, J. Liang, J. Kang, Y. Zhang, T.-L. Ren, and H.-S. P. Wong, “Electrode/oxide interface engineering by inserting single-layer graphene: application for HfOx-based resistive random access memory,” IEEE International Electron Devices Meeting (IEDM) 2012, pp. 489-492, San Francisco, USA.
  253. Y. Wu, S. Yu, H.-S. P. Wong, Y.-S. Chen, H.-Y. Lee, S.-M. Wang, P.-Y. Gu, F. Chen, and M.-J. Tsai, “AlOx-based resistive switching device with gradual resistance modulation for neuromorphic device application,” IEEE International Memory Workshop (IMW) 2012, pp. 111-114, Milan, Italy.
  254. H.-S. P. Wong, X. Guan, D. Kuzum, R. Jeyasingh, and S. Yu, “Variability in emerging memory devices: physical understanding, modeling, and mitigation,” IEEE Workshop on Variability Modeling and Characterization (VMC) 2012, San Jose, USA, invited.
  255. Y. Wu, J. Liang, S. Yu, X. Guan, and H.-S. P. Wong, “Resistive switching random access memory – materials, device, interconnects, and scaling considerations,” IEEE International Integrated Reliability Workshop (IIRW) 2012, Lake Tahoe, USA, invited.
  256. Y. Wu, S. Yu, X. Guan, and H.-S. P. Wong, “Recent progress of resistive switching random access memory (RRAM),” IEEE Silicon Nanoelectronics Workshop (SNW) 2012, Hawaii, USA, invited.
  257. X. Guan, S. Yu, and H.-S. P. Wong, “On the variability of HfOx RRAM: from numerical simulation to compact modeling,” IEEE Workshop on Compact Modeling (WCM) 2012, Santa Clara, CA, USA, invited.
  258. S. Yu, R. Jeyasingh, Y. Wu, and H.-S. P. Wong, “Understanding the conduction and switching mechanism of metal oxide RRAM through low frequency noise and AC conductance measurement and analysis,” IEEE International Electron Devices Meeting (IEDM) 2011, pp. 275-278, Washington DC, USA.
  259. S. Yu, X. Guan, and H.-S. P. Wong, “On the stochastic nature of resistive switching in metal oxide RRAM: physical modeling, Monte Carlo simulation, and experimental characterization,” IEEE International Electron Devices Meeting (IEDM) 2011, pp. 413-416, Washington DC, USA.
  260. S. Yu, Y. Wu, Y. Chai, J. Provine and H.-S. P. Wong, “Characterization of switching parameters and multilevel capability in HfOx/AlOx bi-layer RRAM devices,” International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2011, pp. 106-107, Hsinchu, Taiwan.
  261. Y. Wu, Y. Chai, H.-Y. Chen, S. Yu, and H.-S. P. Wong, “Resistive switching AlOx-based memory with CNT electrode for ultra-low switching current and high density memory application,” Symposium on VLSI Technology (VLSI) 2011, pp. 26-27, Kyoto, Japan.
  262. H.-S. P. Wong, S. Kim, B. Lee, M. A. Caldwell, J. Liang, Y. Wu, R. Jeyasingh, and S. Yu, “Recent progress of phase change memory (PCM) and resistive switching random access memory (RRAM),” IEEE International Memory Workshop (IMW) 2011, pp. 10-14, Monterey, USA, invited.
  263. S. Yu, and H.-S. P. Wong, “Modeling the switching dynamics of programmable-metallization cell (PMC) memory and its application as synapse device for a neuromorphic computation system,” IEEE International Electron Devices Meeting (IEDM) 2010, pp. 520-523, San Francisco, USA.
  264. Y. Chai, Y. Wu, K. Takei, H.-Y. Chen, S. Yu, P. C. H. Chan, A. Javey, and H.-S. P. Wong, “Resistive switching of carbon-based RRAM with CNT electrodes for ultra-dense memory,” IEEE International Electron Devices Meeting (IEDM) 2010, pp. 214-217, San Francisco, USA.
  265. S. Yu, and H.-S. P. Wong, “A phenomenological model of oxygen ion transport for metal oxide resistive switching memory,” IEEE International Memory Workshop (IMW) 2010, pp. 54-57, Seoul, Korea.
  266. H.-S. P. Wong, S. Kim, B. Lee, M. A. Caldwell, J. Liang, Y. Wu, R. Jeyasingh, and S. Yu, “Recent progress of phase change memory (PCM) and resistive switching random access memory (RRAM),” IEEE International Conference on Solid-State and Integrated Circuits Technology (ICSICT) 2010, pp. 1055-1060, Shanghai, China, invited.
  267. Y. Wu, S. Yu, B. Lee and H.-S. P. Wong, “Gradual set and reset in TiN/Al2O3/Pt resistive switching device with sub-20 uA current,” Materials Research Society (MRS) Fall Meeting 2010, paper K4.2, Boston, USA.
  268. S. Yu, Y. Zhao, L. Zeng, G. Du, J. F. Kang, R. Q. Han, and X. Y. Liu, “Variability induced by line edge roughness in double-gate dopant-segregated Schottky MOSFETs,” IEEE Silicon Nanoelectronics Workshop (SNW) 2009, Kyoto Japan, pp.39-40, Kyoto, Japan.
  269. B. Gao, H. W. Zhang, S. Yu, B. Sun, L. F. Liu, X. Y. Liu, Y. Wang, R. Q. Han, J. F. Kang, B. Yu, and Y. Y. Wang, “Oxide-based RRAM: uniformity improvement using a new material-oriented methodology,” Symposium on VLSI Technology (VLSI) 2009, pp. 30-31, Kyoto, Japan.
  270. H. W. Zhang, B. Gao, S. Yu, L. Lai, L. Zeng, B. Sun, L. F. Liu, X. Y. Liu, J. Lu, R. Q. Han, and J. F. Kang, “Effects of ionic doping on the behaviors of oxygen vacancies in HfO2 and ZrO2: a first principles study,” IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 2009, pp. 155-158, San Diego, USA.
  271. S. Yu, Y. Zhao, G. Du, J. F. Kang, R. Q. Han, and X. Y. Liu, “Triple-gate FinFETs with fin-thickness optimization to reduce the impact of fin line edge roughness,” International Conference on Solid State Devices and Materials (SSDM) 2008, pp.440-441, Tsukuba, Japan.
  272. S. Yu, Y. Zhao, Y. Song, G. Du, J. F. Kang, R. Q. Han, and X. Y. Liu, “3-D simulation of geometrical variations impact on nanoscale FinFETs,” IEEE International Conference on Solid-State and Integrated Circuits Technology (ICSICT) 2008. pp.408-411, Beijing, China.
  273. S. Yu, Y. Zhao, G. Du, J. F. Kang, R. Q. Han, and X. Y. Liu, “Impact of stochastic mismatch on FinFETs SRAM induced by process variation,” IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) 2008, paper 4A-3, Hong Kong.
  274. B. Gao, S. Yu, N. Xu, L. F. Liu, B. Sun, X. Y. Liu, R. Q. Han, J. F. Kang, B. Yu, and Y. Y. Wang, “Oxide-based RRAM switching mechanism: A new ion-transport-recombination model,” IEEE International Electron Devices Meeting (IEDM) 2008, pp. 563-566, San Fransisco, USA.
  275. Y. He, Y. Zhao, S. Yu, C. Fan, G. Du, J. F. Kang, R. Q. Han, and X. Y. Liu, “Impact of strain on the performance of Ge-Si core-shell nanowire field effect transistors,” IEEE International Electron Devices Meeting (IEDM) 2008, pp. 189-192, San Fransisco, USA.
  276. Y. Zhao, Y. He, S. Yu, C. Fan, G. Du, J. F. Kang, R. Q. Han, and X. Y. Liu, “Impact of strain on phonon limited mobility in III-V core-shell nanowire,” IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) 2008, paper 6B-3, Hong Kong.
  277. S. Yu, Y. Zhao, Y. Song, G. Du, J. F. Kang, R. Q. Han, and X. Y. Liu, “Full 3-D simulation of gate line edge roughness impact on sub-30nm FinFETs,” IEEE Silicon Nanoelectronics Workshop (SNW) 2008, paper P1-10, Hawaii, USA.