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13 IEDM papers accepted

Our team created a historical record with 13 IEDM papers accepted with our collaborators including Profs. Suman Datta, Asif Khan, and Kai Ni. Below is the list:

  • J. Lee, C. Zhang, S. Park, H. Park, T.-H. Kim, L. J.-C. Liu, E. Ambrosi, M. Song, X. Bao, M.-F. Chang, S. Datta, S. Yu, “Monolithic 3D integration of dual-gated ALD oxide-channel non-volatile capacitive memory on 40nm Si CMOS for digital compute-in-memory,” IEEE International Electron Devices Meeting (IEDM) 2025, San Francisco, USA, highlight paper.
  • M. Shon, S. Lim, S. Yu, “DTCO of multitier CFETs: Ultimate logic and SRAM scaling of A5 technology and beyond,” IEEE International Electron Devices Meeting (IEDM) 2025, San Francisco, USA.
  • O. Phadke, J. Lee, P.-K. Hsu, C. Zhang, A. I. Khan, S. Datta, S. Yu, “Array-level demonstration of charge-domain in-memory search using back-end-of-line compatible ferroelectric nonvolatile capacitors,” IEEE International Electron Devices Meeting (IEDM) 2025, San Francisco, USA.
  • O. Phadke, M. Shon, S. Wodzro, H. Mulaosmanovic, S. Dunkel, S. Beyer, A. I. Khan, Suman Datta, S. Yu, “On the localized ferroelectric phase variation in scaled FeFET: Experiments and modeling,” IEEE International Electron Devices Meeting (IEDM) 2025, San Francisco, USA.
  • S. Deng, J. Sonawane, F. G. Waqar, O. Phadke, C. Zhang, M.-Y. Lee, S. Yu, S. Datta, “Demonstration of 3T0C gain cells with self-aligned oxide transistors for parasitic-aware design at array-level,” IEEE International Electron Devices Meeting (IEDM) 2025, San Francisco, USA.
  • S. Deng, H.-C. Chou, C. Zhang, J. Kwak, A. D. Asokan, E. Quezada, E. Sarkar, J. Lee, J. Shin, D. Chakraborty, V. Sathe, S. Yu, S. Datta, “High-efficiency BEOL-compatible on-chip switched capacitor DC-DC converter using planar and vertical oxide transistors with trench capacitors,” IEEE International Electron Devices Meeting (IEDM) 2025, San Francisco, USA.
  • P. V. Ravindran, Y. Chen, T. O’Neill, H. Chan, H. Jayasankar, P. Ravikumar, Z. Wang, S. Fields, M. Lenox, W. Hubbard, A. Padovani, L. Larcher, G. Thareja, S. Yu, J. Ihlefeld, W. Kim, D. Ha, B. Reagan, A. I. Khan, “Direct observation of nanoscale polarization switching in HZO ferroelectrics using STEM-EBIC,” IEEE International Electron Devices Meeting (IEDM) 2025, San Francisco, USA.
  • H. Park, J. Shin, E. Quezada, H. J. Lee, E. Sarkar, S. Yu, A. I. Khan, S. Guha, W. Haensch, S. Datta, “Fluid imprint: A reliability bottleneck in ferroelectric RAM read operation,” IEEE International Electron Devices Meeting (IEDM) 2025, San Francisco, USA.
  • Y.-H. Kuo, C. Zhang, P. G. Ravikumar, S. Kang, T. Song, M. A. Villena, L. Larcher, H. Kim, M. Hong, P. Yun, G. Thareja, S. Yu, D. Ha, S. Datta, J. E. Medvedeva, A. I. Khan, “Experiments and modeling of defect dynamics and BTI in doped In2O3 TFTs undergoing densification during 400 oC post-BEOL forming gas annealing (FGA),” IEEE International Electron Devices Meeting (IEDM) 2025, San Francisco, USA.
  • E. Sarkar, H. Park, M. A. Al Mamun, H. J. Lee, D. Chakraborty, E. Quezada, C. Zhang, S. Kirtania, M. Tian, A. I. Khan, S. Yu, K. Cho, H. Kim, C. Im, M. Hong, D. Ha, S. Datta, “Overcoming threshold voltage-performance-stability tradeoff with double-gate gallium doped In2O3 MOSFETs using tri-layer HfO2-ZrO2-HfO2 gate stack,” IEEE International Electron Devices Meeting (IEDM) 2025, San Francisco, USA.
  • P. Ravikumar, A. Padovani, C. Park, P. V. Ravindran, M. Desouky, S. Yu, L. Larcher, G. Thareja, K. Kim, K. Seo, K. Kim, W. Kim, D. Ha, A. I. Khan, “Experimental demonstration of robust high temperature operation with 104 endurance and stable Vth at 125 oC enabled by IL scavenging in Si channel FeFETs,” IEEE International Electron Devices Meeting (IEDM) 2025, San Francisco, USA.
  • J. Duan, S. A. Ovy, P.-K. Hsu, Z. Zhao, T. Kampfe, X. Gong, S. Yu, V. Narayanan, S. George, K. Ni, “Securing 3D NAND without density loss via in-situ encryption using a single transistor XOR cell,” IEEE International Electron Devices Meeting (IEDM) 2025, San Francisco, USA.
  • H. J. Lee, H. Park, C. Zhang, J. Shin, E. Sarkar, H. Kim, C. Im, M. Hong, D. Ha, S. Yu, A. I. Khan, S. Datta, “DC and AC PBTI / NBTI analysis for BEOL oxide FETs via on-the-fly measurement and modeling,” IEEE International Electron Devices Meeting (IEDM) 2025, San Francisco, USA.

Prospective students and postdoc researchers

Our lab has very limited quota (likely only one) for PhD research assistant position Fall 2026, please apply for Georgia Tech’s ECE graduate program by the mid-December deadline, and list me as the potential faculty advisor in the application system. https://ece.gatech.edu/future-students/graduate-admissions

Our lab currently does not have any opening for postdoc researchers. Please check back at a later time.

Our lab will host the visiting engineers from our industry sponsors.  

Our lab does NOT accept or host international visiting students or remote interns.

Due to the high volume of inquiry, I may NOT reply to your email if your background does not fit with our on-going research projects.

Prof. Yu is elevated to IEEE Fellow

Prof. Shimeng Yu is elevated to the IEEE Fellow (Class of 2024) for contributions to non-volatile memories and in-memory computing. The nomination came through the Electron Devices Society (EDS) with the support from the Circuits and Systems Society (CASS) and Council on Electronic Design Automation (CEDA).

https://ece.gatech.edu/news/2023/12/ieee-fellow-status-bestowed-upon-durgin-kim-inan-yu-and-zhang