1. NeuroSim
NeuroSim is a circuit-level macro model for benchmarking neuro-inspired ML/AI hardware architectures based on CMOS or emerging memories, which could estimate the circuit-level performance metrics, such as chip area, latency, dynamic energy and leakage power. NeuroSim could be integrated with neural network algorithms to become an integrated framework with hierarchical organization from the device level (transistor and analog synaptic device properties) to the circuit level (array architectures with periphery circuit modules) and then to the algorithm level (neural network topology), enabling trace-based and cycle-accurate evaluation on the accuracy as well as the circuit-level performance metrics at the run-time of learning or inference.
There are multiple versions of NeuroSim, and all source codes are available at GitHub:
- MLP+NeuroSim: The target users are device engineers who wish to quickly estimate the system-level performance with their own synaptic device data including SRAM, RRAM, PCM, STT-MRAM and FeFET with digital row-by-row read-out or analog parallel read-out. As a case study, multilayer perceptron (MLP) and MNIST dataset are used. The integrated MLP+NeuroSim framework is developed in C++ and run in Linux system. The latest released version is V3.0
- DNN+NeuroSim: The target users are circuit/architecture designers who wish to quickly estimate the system-level performance with near-memory or in-memory computing architectures. This is an integration of our NeuroSim circuit macro model with PyTorch within Python environment. User could run hardware-compatible quantized training for accuracy and generate the circuit-level performance inference engine with various device technologies for large-scale dataset (CIFAR and ImageNet) using convolutional neural network topologies (VGG, ResNet and ViT). The latest released version for inference is V1.5 and for training is V2.1
- 3D NeuroSim: This is an extension on top of the DNN+NeuroSim V 1.3 to enable electrical-thermal co-simulation of 3D integrated CIM accelerators. Two types of 3D integration are supported: one is monolithic 3D with back-end-of-line (BEOL) transistors and the other one is heterogeneous 3D with through-silicon-via (TSV) and hybrid bonding. The latest released version for inference is V1.0.
Copyright of the model is maintained by the developers, and the model is distributed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International Public License http://creativecommons.org/licenses/by-nc/4.0/legalcode. If you use this model in your work, you are requested to cite [1] [2] or [3] in the reference.
Developers and contact information:
Ming-Yen Lee, James Read, Junmo Lee, Anni Lu, Xiaochen Peng, Shanshi Huang, Yandong Luo, Pai-Yu Chen, and Shimeng Yu
For technical questions, address to Ming-Yen Lee
For logistic questions, address to Prof. Shimeng Yu
References:
[1] P.-Y. Chen, X. Peng, S. Yu, “NeuroSim+: An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures,” IEEE International Electron Devices Meeting (IEDM) 2017, San Francisco, USA.
[2] P.-Y. Chen, X. Peng, S. Yu, “NeuroSim: A circuit-level macro model for benchmarking neuro-inspired architectures in online learning,” IEEE Trans. CAD, vol. 37, no. 12, pp. 3067-3080, 2018.
[3] X. Peng, S. Huang, Y. Luo, X. Sun, S. Yu, “DNN+NeuroSim: An end-to-end benchmarking framework for compute-in-memory accelerators with versatile device technologies,” IEEE International Electron Devices Meeting (IEDM) 2019, San Francisco, USA.
2. RRAM Verilog-A model for SPICE simulation
The Verilog-A compact model is developed for metal-oxide based RRAM devices with bipolar switching characteristics [1]. It is improved based on the earlier work originally developed at Stanford [2]. The parameters of the model are re-fitted to the experimental data of IMEC HfOx-based RRAM devices [3-4]. This Verilog-A model is compatible with common SPICE simulators, although HSPICE H-2013.03-SP2 is the recommended software. To demonstrate the model, an HSPICE netlist for 1T1R configuration is provided as an example.
Copyright of the model is maintained by the developers, and the model is distributed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International Public License http://creativecommons.org/licenses/by-nc/4.0/legalcode. If you use this model in your work, you are requested to cite [1] in the reference.
Developers and contact information:
Pai-Yu Chen, and Shimeng Yu
For technical/logistic questions, address to Prof. Shimeng Yu
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References:
[1] P.-Y. Chen, S. Yu, “Compact modeling of RRAM devices and its applications in 1T1R and 1S1R array design,” IEEE Trans. Electron Devices, vol. 62, no. 12, pp. 4022-4028, 2015.
[2] X. Guan, S. Yu, and H.-S. P. Wong, “A SPICE compact model of metal oxide resistive switching memory with variations,” IEEE Electron Device Letters, vol. 33, no. 10, pp. 1405-1407, 2012.
[3] Y. Y. Chen, B. Govoreanu, L. Goux, R. Degraeve, A. Fantini, G. S. Kar, D. J. Wouters, G. Groeseneken, J. A. Kittl, M. Jurczak, and L. Altimime, “Balancing SET/RESET pulse for endurance in 1T1R bipolar RRAM,” IEEE Transactions on Electron Devices,vol. 59, pp. 3243-3249, 2012.
[4] Y. Y. Chen, M. Komura, R. Degraeve, B. Govoreanu, L. Goux, A. Fantini, N. Raghavan, S. Clima, L. Zhang, A. Belmonte, A. Redolfi, G. S. Kar, G. Groeseneken, J. A. Kittl and M. Jurczak, “Improvement of data retention in HfO2/Hf 1T1R RRAM cell under low operating current,” IEEE International Electron Devices Meeting (IEDM), pp. 252-255, 2013.